Browsing by Subject "LNA"
Now showing 1 - 2 of 2
Results Per Page
Sort Options
Item Advanced architectures for next generation wireless integrated circuits.(2009-06) Cai, LiuchunIn this thesis, we present and discuss two advanced architectures of wireless integrated circuits. In the first part of this thesis we will focus on the design of an inductorless receiver, which include a LNA, mixer and frequency synthesizer. Inductors are used in RF design to extend the bandwidth by resonating out the load and/or parasitic capacitance. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this thesis we describe a new methodology for designing the RF frontends necessary for the wideband 1GHz-10GHz bandwidth in a 0.13um CMOS technology. To validate our design methodology two receiver RF frontends were designed; a traditional inductor based design and an inductorless design. A common-gate LNA transconductor is followed by a capacitive peaking LNA-mixer pair (CPLM). Measurement results indicate that CPLM with the same bandwidth has better linearity, comparable noise figure and uses only 17% more power. The silicon area for the CPLM is only 22% of the IPLM. Both designs can be mated with an inductorless, ring-oscillator based, wide lock range and low power PLL also shown in this thesis. We present theory and prototype results for injection-locked frequency dividers based on differential ring oscillators (D-ILFD) and single-ended ring oscillators (S-ILFD), which can be locked to all harmonics (i.e., even and odd). We have developed a general theory for lock range and phase noise for all harmonics for both topologies. Measurement results for the D-ILFD and the S-ILFD show that the lock range decreases with increasing harmonics at the low harmonics while leveling off for larger division ratios. Measured integrated phase noise for D-ILFD and S-ILFD also show that the integrated phase noise decreases with increasing harmonics. The measurement results corroborate our theory. Ring oscillator based D-ILFDs and S-ILFDs are compact and consume low power making them well suited for wideband low power PLLs. We exploit the ring VCO based on an updated Maneatis delay cell with self- boosted biased techniques, which has a ultra wide tuning range of 1 GHz to 10.3GHz. The injection-locked frequency divider (ILFD), which can lock to all harmonics, has been used. A wide lock range, low power PLL based ring VCO and ILFD has been designed for UWB radio. Experimental results indicate that integrated phase noise is below a 30 and power consumption is only 8.6 mA to 22.35 mA for the entire frequency bands. In the second part of this thesis, we focus on noise isolation for mixed-signal (RF/analog/digital) design in CMOS 3D ICs. Faraday cages have traditionally been used to provide isolation from electromagnetic fields. In this thesis, we describe the use of Faraday cages for reducing crosstalk in 3D ICs. We validate our methodology with a combination of simulation and measurements from fabricated prototype designs. Measurement and simulation results show that the crosstalk between the transmitter and receiver reduces by about 75dB up to 10GHz by using a Faraday cage in combination with tier-to-tier isolation, which is one of best performance reported so far. Measurement results indicate that the Faraday cages have no effect on the S-parameters and linearity of inductorless RF circuits. We further develop a lumped equivalent model for crosstalk with and without a Faraday cage. There is good agreement between measurement, 3D electromagnetic simulation and lumped circuit simulation.Item CMOS circuits for multi-antenna communication systems.(2010-09) Patnaik, SatwikMulti-antenna systems allow for higher communication rates without substantial increase in hardware and power. This has led to significant interest in incorporating multi-antenna communication into upcoming wireless standards, like the 802.11n. This thesis focuses on CMOS circuits and architectures for multi-antenna wireless communication systems. Specifically, we will propose solutions for a special class of multi-antenna systems called phased-array systems. The most important circuit block in a phased-array system is the phase-shifter. Traditional phased-array systems, mostly military radars, used external ferrite phase-shifters for microwave applications, which were wide-band, almost noiseless, highly linear and had high power-handling capability, but were bulky. Commercial wireless systems rely on portability and low-power, with the result that CMOS is the technology of choice and most products are fully integrated on a single-chip. On-chip CMOS phase-shifters have not been able to match the performance of ferrite phase-shifters. Consequently, CMOS-based phased-array systems have relied on a modified architecture known as the LO-phase shifting architecture to deliver comparable performance. In this work, we first present two novel schemes for the phase-generation network for the LO-phase-shifting architecture, based on a phenomenon called injection-locking. The injection-locked oscillator (ILO) is used as a phase-shifter. The two schemes are integrated into a dual-mode architecture for a phased-array receiver providing us with the advantages of both. The prototype, operating at 2.4-GHz, is fabricated in a 0.13-μm CMOS technology. It requires lower power and area compared to previous state-of-the-art designs. Measurement results from this prototype show excellent agreement with the theoretical performance predicted for the phased-array receiver. Both architectures have also been extended to two-dimensional phased-array systems. A majority of the commercial phased-array applications are focused on the mm-wave regime. We have verified that our architecture can operate at these frequencies as well. A 24-GHz two-channel CMOS phased-array receiver has been designed and fabricated in 0.13-μm BiCMOS technology. In this architecture, the injection-locked oscillator not only acts as a phase-shifter and buffer, but also as a frequency tripler. Because of this multi-functionality of the ILO, the overall area and power of this receiver are better than other state-of-the-art designs. Since the LO distribution network now operates at one-third the LO frequency, it allows for further power savings in the distribution network. Finally, a beam-forming receiver based on the Fast-Fourier Transform (FFT) is presented. In this architecture, the beam-forming operations are performed in the baseband processing section. Owing to a low-power FFT architecture and the inherent properties of the FFT, multiple beams can be created at closely-spaced frequencies. This allows the use of narrow-band transmitter and receiver architectures for the RF section. A two-channel receiver based on this architecture has been designed in a 65-nm CMOS process. In addition, to these different receiver architectures, a novel 24-GHz UWB-LNA is presented. The LNA, which has been integrated as part of a UWB receiver, is presented in this thesis. However, the overall UWB receiver design is not presented here.