Browsing by Subject "Jitter"
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Item Crosstalk mitigation techniques in high-speed serial links.(2009-04) Sham, Kin-JoeOne of the primary challenges in high-speed chip-to-chip serial link design is maintaining signal integrity in the presence of inter-symbol interference and crosstalk. Far-end crosstalk (FEXT), the interference from an adjacent aggressor line, has become a major noise source as data rates continue to increase. In addition to reducing the effective signal-to-noise and interference ratio (SNIR), FEXT introduces deterministic crosstalk-induced jitter (CIJ) in the received signal, thereby degrading the receiver's bit error rate (BER). By mitigating FEXT, inter-chip I/Os can have higher aggregate data throughput and interconnects can be placed closer together, which reduces the board area needed and the cost associated with it. In this thesis, two different techniques have been proposed to mitigate the effect of FEXT. The first technique employs FIR filters to implement FEXT cancellation (XTC) at the transmit end, which removes FEXT on each channel to further improve the SNIR of the received data and reduce the CIJ. The second technique staggers the multilane I/Os by adding a variable delay to every other channel at the transmit end, thus shifting the coupled FEXT away from the zero-crossing points of the victim channel. Although I/O staggering can lower CIJ and increase timing margin with relatively little added power, it comes at a cost of decreasing the existing voltage margin. The proposed techniques provide the required groundwork for developing MIMO communication methods that will effectively extricate additional information from FEXT to further reduce the BER during data detection. New I/O transceiver designs with the two techniques have been implemented and fabricated in CMOS processes. In addition, an accurate FEXT model has been developed using a two-pole moment matching technique. As data rates approach higher speeds and FEXT becomes a dominant noise source, the research presented has shown that FEXT mitigation is critical to enhance jitter performance and improve eye openings in high-speed serial links.Item Jitter Suppression Techniques for High Speed Communication Systems(2019-12) Jamalizavareh, ShivaThe drive towards fast and robust communication has resulted in an increased focus on high frequency analog and digital transceivers. One of the major challenges in high-speed analog transceivers, is the front-end analog-to-digital converter (ADC). All ADCs rely on periodic samples of the input signal. To enable high accuracy analog to digital conversion at high frequencies, a clean sampling clock is required. However, the non-idealities in the clock generation and distribution system can result in uncertainties in the sampling edges of the clock signal. These uncertainties are referred to as jitter. In many cases, the jitter requirement on the sampling clock is less than 100 fs, rms, realizing which is not trivial. More important, there exists a disconnect between the clock designers and the ADC designers, when it comes to jitter suppression. While clock designers are focused on minimizing the narrow-band clock jitter, the ADC designers have to deal with the broadband noise in the clock path, which is detrimental to the ADC's performance. The question we try to answer in this thesis is, whether rather than tackling the jitter at the source, one can reduce the jitter sensitivity of the ADCs by using jitter-resilient sampling techniques. A review of various sources of jitter, and the impact of jitter on analog and digital transceivers is presented. This facilitates the understanding, characterizing, and ultimately reducing the jitter-induced errors in the communication systems. A new sampling technique, called Delta Sigma sampling, is proposed to suppress the jitter induced sampling error in ADCs. The design uses a Delta Sigma architecture with low oversampling ratio (OSR) to shape the jitter error, in the same way that a Delta Sigma ADC shapes the quantization error. The Delta Sigma sampler, however, does not have a quantizer, and as a result, the output of the sampler is a sampled-and-held signal. Therefore, a Delta Sigma sampler can be used as a jitter-resilient front-end for any type of ADC. To prove the functionality of the proposed sampling technique, a comprehensive time-domain analysis is presented. In this analysis, 1st-, 2nd-, and higher order Delta Sigma samplers with various feedback architectures are considered. The feedback architectures include return-to-zero (RZ), non return-to-zero (NRZ), and switched-capacitor. Three sources of jitter are identified in the sampler: the sampling clock jitter, the feedback pulse edge jitter, and the feedback pulsewidth variations. We show that first, the switched-capacitor feedback impairs the jitter shaping properties of the loop. In fact, the decaying nature of the pulse reduces the loop order to N-1. Second, a 1st-order Delta Sigma sampler has the same signal-to-jitter noise ratio (SJNR) with switched-capacitor feedback, and with constant-pulsewidth RZ feedback. RZ feedback relaxes the slew rate requirements of the integrator, thereby reducing the power consumption of the system. However, the feedback pulsewidth variations degrade the SJNR significantly. A new clocking scheme, called correlated clocking, is introduced to alleviate the pulsewidth jitter of the RZ feedback. This technique uses the correlation between the rising and falling edges of the feedback clock to minimize the feedback pulsewidth variations. The proposed clocking technique can also be used in continuous-time Delta Sigma ADCs. The analysis indicates that the maximum SJNR benefit of a Delta Sigma sampler over a Nyquist sampler is equal to 10*log10(OSR)+4.77 dB. That is equivalent to a 4X reduction of clock jitter in a Nyquist sampler or 3X increase in OSR for an oversampler. The maximum SJNR is independent of the loop order and the feedback architecture, and it stays constant for OSR >5. Finally, we show that in contrary to the common belief, the feedback edge jitter dominates the overall jitter in the 2nd- and higher-order samplers, as it translates into feedback pulsewidth variations at the output of the second integrator. This error gets 1st-order shaped, regardless of the loop order, making it the dominant source of jitter in higher order Delta Sigma loops. The theoretical analysis is veried by numerical simulations in MATLAB and behavioral simulations in Cadence. In addition, a 5 GS/s 1st-order Delta Sigma sampler with correlated clocking is implemented in 65 nm CMOS technology, and verified through circuit-level simulations in Cadence.Item System and Media Optimizations for improved HAMR Performance(2020-08) Natekar, NiranjanIt is said that data never sleeps. It has a ubiquitous presence and is being generated at an exceptional pace from different sources. The insurmountable demand for data must be met with an equally fast paced data supply which has led to the development of data servers by companies like Microsoft and Google. In spite of facing an existential crisis due to the development of SSD’s, the Compound Annual Growth Rate (CAGR) of ~ 40% maintained by the HDD industry has ensured that these devices are a necessity when it comes to large scale data storage. The growth of the HDD industry is helped by the fact that a huge amount of research is dedicated to developing new data recording technologies to improve the storage capacity of HDD’s. Significant investment has gone into developing a new data recording technology called Heat Assisted Magnetic Recording (HAMR) that is expected to improve the storage density up to at least 5Tb/in2. In conjunction with other improvements (like the development of Bit Patterned Media BPM), the expected density output for HAMR can be even higher. The optimization of the HAMR technology has focused on different aspects of the HAMR system, optical, magnetic, mechanical and electrical. In this thesis, different system and media optimizations that may help improve the HAMR performance are explored. The effect of doped L10 FePt media, which is an extremely popular HAMR media, is considered to understand how a change in its Curie temperature (Tc) can actually influence its intrinsic magnetic properties. This is followed by the implementation of micromagnetic simulations with the use of the stochastic Landau Lifshitz Gilbert (LLG) equation that is used to mimic the magnetization dynamics of grains. These simulations are used to vary the media properties and HAMR process parameters to optimize a thin 3nm (write layer)/6nm (storage layer) Thermal Exchange Coupled Composite (ECC) HAMR media. Introducing finite exchange coupling between the grains of the write layer and scaling the damping in the write layer are techniques that can help reduce the DC noise and improve the Signal to Noise Ratio (SNR). The Ensemble Waveform Analysis technique identifies Transition SNR as the main cause of SNR variation. This optimization process lends credence to the idea that a thinner composite media may be used to realize significant enhancements of SNR. Micromagnetic simulations are also used to address an important issue related to HAMR; the high temperature for writing data can cause heating issues with long term HAMR use. A low temperature Thermal ECC media is proposed that can significantly reduce the writing temperature (by about 34%) and that can reduce the peak temperature of the heat spot used to heat the media in the HAMR process by 200K. This is followed by an analytical formulation that is derived to calculate the transition jitter in the HAMR process. The jitter is known to depend on the grain size as well as the heat spot thermal gradient. It also depends on the Voronoi Grain Size Distribution, as well as exhibiting a surprising nonlinear dependence on the reader width. By combining the noise due to these dependencies the analytical formulation can be derived. This simple formulation provides both physical insight and conserves computational time relative to lengthy (and complex) recording simulations. A detailed analysis of the Adjacent Track Erasure (ATE) in the HAMR process is also explored. The numerical extent of ATE in different HAMR media is established and techniques are implemented using micromagnetic simulations in an attempt to reduce the ATE effect. A hypothesis is established to explain the presence of extent of ATE in different HAMR media. Research in the area of HAMR process and system optimization is of huge importance especially since the data storage industry has invested a lot in terms of research and manpower in this technology. Potential directions of research include techniques to reduce the ATE, improving the designs of different HAMR system components and developing better data post processing techniques like Neural Networks and 2D detectors.