Browsing by Subject "In-situ"

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    Analytical and Experimental Nanomechanical Approaches to Understanding the Ductile-to-Brittle Transition
    (2015-10) Hintsala, Eric
    This dissertation presents progress towards understanding the ductile-to-brittle transition (DBT) using a mixture of nanomechanical experiments and an analytical model. The key concept is dislocation shielding of crack tips, which is occurs due to a dislocation back stress. In order to properly evaluate the role of these interactions, in-situ experiments are ideal by reducing the number of interacting dislocations and allowing direct observation of cracking behavior and the dislocations themselves. First, in-situ transmission electron microscope (TEM) compression experiments of plasma-synthesized silicon nanocubes (NCs) are presented which shows plastic strains greater than 50% in a semi-brittle material. The mechanical properties are discussed and plasticity mechanisms are identified using post-mortem imaging with a combination of dark field and high-resolution imaging. This observations help to develop a back stress model which is used to fit the hardening regime. This represents the first study of its kind where back stresses are used in a discrete manner to match hardening rates. However, the important measurable quantities for evaluating the DBT include fracture toughness values and energetic activation parameters for cracking and plasticity. In order to do this, a new method for doing in-situ fracture experiments is explored. This method is pre-notched three point bending experiments, which were fabricated by focused ion beam (FIB) milling. Two different materials are evaluated: a model ductile material, Nitronic 50, an austenitic steel alloy, and a model brittle material, silicon. These experiments are performed in-situ scanning electron microscope (SEM) and TEM and explore different aspects including electron backscatter diffraction (EBSD) to track deformation in SEM scale experiments, pre-notching using a converged TEM beam to produce sharper notches better replicating natural cracks, etching procedures to reduce residual FIB damage and elevated temperature experiments. Lastly, an analytical method to predict DBTs is presented which can account for effects of strain rate, temperature and impurity presence. The model is tested by pre-existing data on macroscopic compact tension specimens of single crystal Fe-3%Si. Next, application of the model to nano/micro scale fracture toughness experiments is explored and the large number of confounding variables is discussed in detail. A first attempt at fitting is also presented.
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    Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors
    (2016-11) Kundu, Somnath
    Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V.