Browsing by Subject "HPC"

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    The Applications of Workload Characterization in The World of Massive Data Storage
    (2015-08) He, Weiping
    The digital world is expanding exponentially because of the growth of various applications in domains including scientific fields, enterprise environment and internet services. Importantly, these applications have drastically different storage requirements including parallel I/O performance and storage capacity. Various technologies have been developed in order to better satisfy different storage requirements. I/O middleware software, parallel file systems and storage arrays are developed to improve I/O performance by increasing I/O parallelism at different levels. New storage media and data recording technologies such as shingled magnetic recording (SMR) are also developed to increase the storage capacity. This work focuses on improving existing technologies and designing new schemes based on I/O workload characterizations in corresponding storage environments. The contributions of this work can be summarized into four pieces, two on improving parallel I/O performance and two on increasing storage capacity. First, we design a comprehensive parallel I/O workload characterization and generation framework (called PIONEER) which can be used to synthesize a particular parallel I/O workload with desired I/O characteristics or precisely emulate a High Performance Computing (HPC) application of interest. Second, we propose a non-intrusive I/O middleware (called IO-Engine) to automatically improve a given parallel I/O workload in Lustre which is a widely used HPC or parallel I/O system. IO-Engine can explore the correlations between different software layers in the deep I/O path, as well as workload patterns at runtime to transparently transform the workload patterns and tune related I/O parameters in the system. Third, we design several novel static address mapping schemes for shingled write disks (SWDs) to minimize the write amplification overhead in hard drives adopting SMR technology. Fourth, we propose a track-level shingled translation layer (T-STL) for SWDs with hybrid update strategy (in-place update plus out-of-place update). T-STL uses dynamic address mapping scheme and performs garbage collection operations by migrating selected disk tracks. This scheme can provider larger storage capacity and better overall performance with the same effective storage percentages when compared to the static address mapping schemes.
  • Thumbnail Image
    Item
    Enhancing Performance Evaluation and Characterization Techniques to I dentify Performance Changes in High-Performance Computing Systems
    (2021-11) huerta, yectli
    High Performance Computing systems are complex and require a lot of effort to tune the system to achieve peak performance. Performance analysis is a time consuming process. The goal of this thesis is to understand the effects changes to the system or compiler configuration had on performance and how it is reflected in CPU performance metrics. This thesis presents two approaches to enhance the evaluation process of HPC systems. First, a process that makes it possible to systematically and efficiently search the parameter space to find an optimal configuration of a benchmark with a large number of tunable parameters is introduced. The search for an optimal combination of parameters can be daunting, especially when it involves high dimensionality of mixed type categorical and continuous variables. This thesis shows that through the use of statistical techniques, a systematic and efficient search of the parameter space can be conducted. These techniques can be applied to variables that are categorical or continuous in nature and do not rely on the standard assumptions of linear models, namely that the response variable can be described as a linear combination of the regression coefficients. Second, a normalization technique that will make it possible to identify relative differences between performance metrics to better understand the effects changes had on the underlying system is presented. The use of Top-Down microarchitecture analysis method makes it possible to understand how pipeline bottlenecks were affected by changes in the system configuration, or compiler version. Bottleneck analysis makes it possible to better understand how different hardware resources are being utilized, highlighting portions of the CPU's pipeline where possible improvements could be achieved. The Top-Down analysis method is complemented with the use a normalization technique from the field of economics, purchasing power parity (PPP), to better understand the relative difference between changes. This thesis showed that system changes had effects that sometimes were not reflected on the corresponding Top-Down metrics. The use of the PPP normalization technique made it possible to highlight differences and trends in bottleneck metrics, differences that standard techniques based in absolute, non-normalized, metrics failed to highlight.