Browsing by Subject "FinFET"

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    Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes
    (2018-05) Kumar, Saurabh
    Soft errors induced by particle strikes have been a major concern in reliability critical applications such as defense, space, medicine and finance etc. A number of radiation particles present in the ambient environment can induce errors in circuits which can result in system failure. These can be charged particles such as alpha, electrons, protons or heavy ions or neutral particles like neutrons, laser etc. Radioactive impurities like Uranium and Thorium in chip and packaging materials emit alpha particles that contribute towards errors. Protons, electrons and neutrons are found in space and terrestrial environment that can induce soft errors. When these particles penetrate the silicon, electron hole pairs are generated along the tracks that may be collected by the p-n junctions via drift and diffusion mechanisms. If the collected charge is large enough, the logic state of the junction may change, resulting in what we refer to as a soft error. Continuous process scaling has resulted in shrinking of device features that results in smaller junction area and lower strike probability at or around the junction that can lead to an error induction. The transistors, therefore, have become more and more resilient towards radiation-induced strikes. Advent of FinFET technology has further increased the resilience of devices towards soft errors by employing narrow three dimensional source-drain features that inherently make it difficult for the charge to get collected quickly. However, with process scaling, device density per die has gone up exponentially which means more transistors can be packed in the same die area. This has resulted in a probable rise in overall soft error rate (SER) due to increased number of susceptible nodes. Hence although per device SER has gone down, chip-level SER still remains a critical reliability issue that needs to be dealt with. In order to come up with efficient circuit designs that are immune towards soft errors, it is necessary to accurately and efficiently characterize SER in the given process. In this work, novel circuits have been proposed that capture important circuit parameters impacting SER. First of these is the Back-Sampling Chain (BSC) circuit that employs highly sensitive detection chains with more than 9x sensitivity as compared to conventional circuits. Higher sensitivity is critical in SER characterization since it facilitates higher strike induction resulting in collection of large data in limited beam time. BSC chain is capable of detecting Single Event Transients (SETs), Single Event Upsets (SEUs) and Multi-Bit-Upsets (MBUs), with scalable architecture that can be scaled to millions of stages without compromising on the measurement accuracy. BSC circuit can measure the SET pulse parameters (width and amplitude) while sweeping the sensitivity points that helps in re-construction of individual strike pulses. This, to our knowledge, is the first work to show individual pulse re-construction. Secondly, we show the detailed analysis of neutron-induced soft errors measured from the flip-flop arrays implemented in 14nm FinFET CMOS. Depending on the strike location and circuit topology, the MBU patterns may differ which has been characterized and a qualitative first order analysis has been presented. Seven unique MBU patterns extracted from measured data have been studied and analyzed to find layout dependencies on MBU. Results show strong correlation between the inter-node proximity and MBUs. With lower proximity, MBU induction probability as well as MBU size goes up and vice versa. The multi-cell-cluster (MCU) analysis shows higher SER cross-section for smaller MCU cluster size while the bigger clusters have lower contribution towards overall MBU SER. Thirdly, a 14nm test chip employing a novel NAND/NOR readout chain for characterizing SER in combinational logic gates is proposed. The proposed test structure uses high density standard logic gates as detection circuit for sensing SETs that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.
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    Performance variations due to layout-dependent stress in VLSI circuits
    (2015-05) Marella, Sravan
    Layout-dependent stress is a significant source of variability in advanced VLSI technologies that impacts circuit performance. Mechanical stress affects transistor electrical parameters mobility and threshold voltage due to piezoresistivity and stress-induced band deformation, respectively. Unintentional sources of mechanical stress and intentional stress variability cause device performance to depend upon the underlying layout topology and its location in the layout. Advanced packaging technologies have exacerbated this class of variability by introducing new set of unintentional stresses in the layout. Consequently, circuit performance becomes highly placement dependent. The traditional paradigm of using pessimistic margins to account for variations can make meeting stringent design specifications a daunting task. Thus, it is imperative to capture the effects of layout dependent stress during circuit analysis. Evaluating circuit performance involves modeling the stress distributions in the layout accurately and translating the mechanical abstraction of the layout to circuit-level abstraction. This thesis develops scalable techniques to characterize the layout-dependent stress effects to quantify the ensuing circuit-level variations in path delays and leakage power. Based on this analysis, layout optimization strategies are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit performance variations. Thermal-stress effects are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. Analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing and leakage power consumption. A biaxial stress model is built, based on a superposition of 2D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate changes in transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performance induced by TSV stress. Finally, layout guidelines are presented that optimize circuit delays in 3D-ICs. Thermal stresses from shallow trench isolation (STI) are another major source of unintentional stress that affect bulk planar transistors in conventional and 3D integrated circuits. STI is employed to electrically isolate transistors and the amount of STI surrounding an active region depends upon the location of the neighboring transistors in the layout. An analytical model based on inclusion theory in micromechanics is employed to accurately estimate the biaxial stresses and the strains induced in the active region by the surrounding STI in the layout. The induced changes in mobility and threshold voltage changes are computed at the transistor level and then propagated to the gate and circuit levels to predict circuit-level delay and leakage power for a given placement. For 3D-ICs, the combined effects of STI and TSV are evaluated. In bulk technologies, intentional source/drain stressors are used to enhance transistor performance. In FinFET technologies, these stressors lose their effectiveness with reducing contacted gate pitch. Moreover, owing to the three dimensional nature of the FinFETs, the beneficial stress relaxes along the free-edges of standard cell layouts. Thus, the magnitudes of engineered mechanical stress depend upon the underlying layout topology. To improve circuit performance, a dual gate pitch technique is proposed, where standard cells with twice the gate pitch are selectively used on the gates of the circuit critical paths, at minimal area and power costs. A stress-aware library characterization is performed for FinFET-based standard cells by obtaining stress distributions using finite element simulations on a subset of structures. The stresses are then employed to create look-up tables for mobility multipliers and threshold voltage shifts, for subsequent performance characterization of FinFET-based standard cells. Finally, a circuit delay optimizer is applied using the dual gate pitch approach and is compared with an alternative gate sizing approach in 14nm/10nm/7nm technologies. Using a combination of gate sizing and the dual gate pitch approach, it is shown that the power delay product of FinFET-based circuits can be improved.