Browsing by Subject "Energy reduction"

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    Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing
    (2015-06) Srinath, Vinayak Bhargav
    A processor's power consumption can be most efficiently reduced by lowering the supply voltage. But with reduced voltage levels comes the major concern of failure of memory circuits. ASIC designers define a minimum operable voltage of the processor's on-chip cache often referred to as the Vccmin which is the voltage level below which the processor's memory-subsystem is no longer reliable. This guard-banding mechanism adds an additional overhead on the processor's memory-subsystem which does not allow it to operate below this voltage, and its important to note that the processor's memory-subsystem is one of the major contributors of its overall energy consumption. Guard-banding mechanisms are not just limited to increased minimum operable voltages and they result in large overheads. If certain restrictions are relaxed on the reliability of the output we can obtain significant savings in energy by eliminating these guard-banding mechanisms. This work explores different configurations of architectures suitable for low voltage operation of image and video applications by outlining the energy, accuracy, area and performance trade-offs.