Browsing by Subject "Digital signal processing"
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Item Digital logic and signal processing computations with molecular reactions.(2012-05) Jiang, HuaJust as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (em molecules per unit volume). Broadly, the field strives for molecular implementations of computational processes -- that is to say processes that transform input concentrations of chemical types into output concentrations of chemical types. In this dissertation, we present methodologies to implement digital signal processing (DSP) operations, such as filtering and signal transformation, and digital logic operations, such as latching and flip-flopping, with molecular reactions. Molecular reactions that produce time-varying output quantities of molecules as a function of time-varying input quantities are designed according to a DSP or logic specification. Unlike all previous schemes for molecular computation, the methodology produces designs that are dependent only on coarse rate categories for the reactions ("fast" and "slow"). Given such categories, the computation is exact and independent of the specific reaction rates. We first present a methodology for implementing DSP through a globally synchronous, locally asynchornous scheme we call the RGB scheme. We then present a general methodology for implementing synchronous sequential computation. We generate a four-phase clock signal through robust, sustained chemical oscillations. We implement memory elements by transferring concentrations between molecular types in alternating phases of the clock. Thirdly, we propose a general methodology for implementing asynchronous sequential computation, including a method to schedule data flow for feed-forward systems and a method to implement systems with feedback loops. Finally, we present a methodology for systematic synthesis of various types of sequential digital logic. Given a system specification, a chemical reaction network is synthesized to perform the input/output logic functions. Synthesized systems are concise and robust in that computation accuracy does not depend on specific values of rate constants. All designs are mapped into DNA strand displacement reactions and validated through transient simulations of the chemical kinetics at the DNA reactions level.Item Digital Signal Processing and Machine Learning System Design using Stochastic Logic(2017-07) Liu, YinDigital signal processing (DSP) and machine learning systems play a crucial role in the fields of big data and artificial intelligence. The hardware design of these systems is extremely critical to meet stringent application requirements such as extremely small size, low power consumption, and high reliability. Following the path of Moore's Law, the density and performance of hardware systems are dramatically improved at an exponential pace. The increase in the number of transistors on a chip, which plays the main role in improvement in the density of circuit design, causes rapid increase in circuit complexity. Therefore, low area consumption is one of the key challenges for IC design, especially for portable devices. Another important challenge for hardware design is reliability. A chip fabricated using nanoscale complementary metal-oxide-semiconductor (CMOS) technologies will be prone to errors caused by fluctuations in threshold voltage, supply voltage, doping levels, aging, timing errors and soft errors. Design of nanoscale failure-resistant systems is currently of significant interest, especially as the technology scales below 10 nm. Stochastic Computing (SC) is a novel approach to address these challenges in system and circuit design. This dissertation considers the design of digital signal processing and machine learning systems in stochastic logic. The stochastic implementations of finite impulse response (FIR) and infinite impulse response (IIR) filters based on various lattice structures are presented. The implementations of complex functions such as trigonometric, exponential, and sigmoid, are derived based on truncated versions of their Maclaurin series expansions. We also present stochastic computation of polynomials using stochastic subtractors and factorization. The machine learning systems including artificial neural network (ANN) and support vector machine (SVM) in stochastic logic are also presented. First, we propose novel implementations for linear-phase FIR filters in stochastic logic. The proposed design is based on lattice structures. Compared to direct-form linear-phase FIR filters, linear-phase lattice filters require twice the number of multipliers but the same number of adders. The hardware complexities of stochastic implementations of linear-phase FIR filters for direct-form and lattice structures are comparable. We propose stochastic implementation of IIR filters using lattice structures where the states are orthogonal and uncorrelated. We present stochastic IIR filters using basic, normalized and modified lattice structures. Simulation results demonstrate high signal-to-error ratio and fault tolerance in these structures. Furthermore, hardware synthesis results show that these filter structures require lower hardware area and power compared to two's complement realizations. Second, We present stochastic logic implementations of complex arithmetic functions based on truncated versions of their Maclaurin series expansions. It is shown that a polynomial can be implemented using multiple levels of NAND gates based on Horner's rule, if the coefficients are alternately positive and negative and their magnitudes are monotonically decreasing. Truncated Maclaurin series expansions of arithmetic functions are used to generate polynomials which satisfy these constraints. The input and output in these functions are represented by unipolar representation. For a polynomial that does not satisfy these constraints, it still can be implemented based on Horner's rule if each factor of the polynomial satisfies these constraints. format conversion is proposed for arithmetic functions with input and output represented in different formats, such as $\text{cos}\,\pi x$ given $x\in[0,1]$ and $\text{sigmoid(x)}$ given $x\in[-1,1]$. Polynomials are transformed to equivalent forms that naturally exploit format conversions. The proposed stochastic logic circuits outperform the well-known Bernstein polynomial based and finite-state-machine (FSM) based implementations. Furthermore, the hardware complexity and the critical path of the proposed implementations are less than the Bernstein polynomial based and FSM based implementations for most cases. Third, we address subtraction and polynomial computations using unipolar stochastic logic. It is shown that stochastic computation of polynomials can be implemented by using a stochastic subtractor and factorization. Two approaches are proposed to compute subtraction in stochastic unipolar representation. In the first approach, the subtraction operation is approximated by cascading multi-levels of OR and AND gates. The accuracy of the approximation is improved with the increase in the number of stages. In the second approach, the stochastic subtraction is implemented using a multiplexer and a stochastic divider. We propose stochastic computation of polynomials using factorization. Stochastic implementations of first-order and second-order factors are presented for different locations of polynomial roots. From experimental results, it is shown that the proposed stochastic logic circuits require less hardware complexity than the previous stochastic polynomial implementation using Bernstein polynomials. Finally, this thesis presents novel architectures for machine learning based classifiers using stochastic logic. Three types of classifiers are considered. These include: linear support vector machine (SVM), artificial neural network (ANN) and radial basis function (RBF) SVM. These architectures are validated using seizure prediction from electroencephalogram (EEG) as an application example. To improve the accuracy of proposed stochastic classifiers, an approach of data-oriented linear transform for input data is proposed for EEG signal classification using linear SVM classifiers. Simulation results in terms of the classification accuracy are presented for the proposed stochastic computing and the traditional binary implementations based datasets from two patients. It is shown that accuracies of the proposed stochastic linear SVM are improved by 3.88\% and 85.49\% for datasets from patient-1 and patient-2, respectively, by using the proposed linear-transform for input data. Compared to conventional binary implementation, the accuracy of the proposed stochastic ANN is improved by 5.89\% for the datasets from patient-1. For patient-2, the accuracy of the proposed stochastic ANN is improved by 7.49\% by using the proposed linear-transform for input data. Additionally, compared to the traditional binary linear SVM and ANN, the hardware complexity, power consumption and critical path of the proposed stochastic implementations are reduced significantly.Item Efficient VLSI Architectures for High-Speed Ethernet Transceivers(2008-08) Chen, JieThis thesis investigates efficient VLSI architectural design aspects of a digital signal processing (DSP) transceiver in high speed multi-pair wireline communication systems, such as 10 Gigabit Ethernet over copper (10GBASE-T), with the goal to reduce the hardware complexity and power consumption of various DSP components while maintaining the speed and performance requirements. The covered topics mainly include efficient far-end crosstalk (FEXT) cancellers, novel multi-input multi-output (MIMO) equalizers combined with Tomlinson-Harashima Precoding (THP), low complexity echo and near-end crosstalk (NEXT) cancellers. A novel feedforward delayed FEXT canceller in a THP based system is developed to remove FEXT as noise. Unlike conventional techniques on FEXT cancellation, the proposed FEXT canceller can mitigate the non-causal part of FEXT; thus it can achieve better cancellation performance. In addition, a modified design is developed by eliminating the feedback loops in the FEXT cancellers such that the resulting feedforward FEXT canceller is suitable for high speed applications. FEXT has been found to contain information about the symbols transmitted from remote transmitters and thus MIMO equalization technique is proposed to jointly process ISI and FEXT such that the useful information in FEXT can be utilized. It is shown that the proposed architecture overcomes the limitation of the traditional equalization schemes and can achieve a better system performance and lower hardware complexity. A computationally efficient approach for calculating the optimal tap coefficients of MIMO equalizers and cancellers is also proposed to speedup the computation. Furthermore, a practical equalization scheme which combines the MIMO equalization technique and TH precoding technique is proposed for the real application of high speed Ethernet systems. Different from existing work on MIMO equalization, the proposed scheme exactly complies with the current 10GBASE-T standard and can be easily pipelined for high speed implementation. Hardware complexity reduction schemes by utilizing the increased decision point SNR (DP-SNR) are also considered. Gigabit and multi-gigabit transceivers require very long adaptive filters for echo and NEXT cancellation. Implementation of these filters not only occupies large silicon area but also consumes significant power. This thesis considers the problems of designing cost-efficient echo and NEXT cancellers mainly from two different aspects: one is to reduce the number of taps used in these noise cancellers; the other is to reduce the word-length used to represent data in a VLSI system. First, the sparse characteristics of the echo and NEXT channel impulse responses is exploited to reduce computational cost of adaptive echo and NEXT cancellers. Second, a novel word-length reduction scheme is proposed by replacing the original input to the echo and NEXT cancellers with a finite-level signal, which is then recoded to have shorter word-length. To further reduce the complexity of these cancellers, an improved design is proposed by exploiting the property of the compensation signal. Compared with the traditional design, the proposed echo and NEXT cancellers have exact input and do not suffer from the quantization problem, and thus they are more suitable for VLSI implementation. The design issues of adaptive noise cancellers by using the proposed word-length reduction method are also considered and modified designs of the adaptive cancellers are developed to further reduce the overall hardware cost of echo and NEXT cancellers with acceptable cancellation performance. Finally, the design approach for stable pole-zero modeling of long finite impulse response (FIR) filters is proposed.Item A Framework for Computing Discrete-Time Systems and Functions using DNA(2017-07) Salehi, sayed ahmadDue to the recent advances in the field of synthetic biology, molecular computing has emerged as a non-conventional computing technology. A broad range of computational processes has been considered for molecular implementation. In this dissertation, we investigate the development of molecular systems for performing the following computations: signal processing, Markov chains, polynomials, and mathematical functions. First, we present a \textit{fully asynchronous} framework to design molecular signal processing algorithms. The framework maps each delay unit to two molecular types, i.e., first-type and second-type, and provides a 4-phase scheme to synchronize data flow for any multi-input/multi-output signal processing system. In the first phase, the input signal and values stored in all delay elements are consumed for computations. Results of computations are stored in the first-type molecules corresponding to the delay units and output variables. During the second phase, the values of the first-type molecules are transferred to the second-type molecules for the output variable. In the third phase, the concentrations of the first-type molecules are transferred to the second-type molecules associated with each delay element. Finally, in the fourth phase, the output molecules are collected. The method is illustrated by synthesizing a simple finite-impulse response (FIR) filter, an infinite-impulse response (IIR) filter, and an 8-point real-valued fast Fourier transform (FFT). The simulation results show that the proposed framework provides faster molecular signal processing systems compared to prior frameworks. We then present an overview of how continuous-time, discrete-time and digital signal processing systems can be implemented using molecular reactions. We also present molecular sensing systems where molecular reactions are used to implement analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). These converters can be used to design mixed-signal processing molecular systems. A complete example of the addition of two molecules using digital implementation is described where the concentrations of two molecules are converted to digital by two 3-bit ADCs, and the 4-bit output of the digital adder is converted to analog by a 4-bit DAC. Furthermore, we describe implementation of other forms of molecular computation. We propose an approach to implement any first-order Markov chain using molecular reactions in general and DNA in particular. The Markov chain consists of two parts: a set of states and state transition probabilities. Each state is modeled by a unique molecular type, referred to as a data molecule. Each state transition is modeled by a unique molecular type, referred to as a control molecule, and a unique molecular reaction. Each reaction consumes data molecules of one state and produces data molecules of another state. The concentrations of control molecules are initialized according to the probabilities of corresponding state transitions in the chain. The steady-state probability of the Markov chain is computed by the equilibrium concentration of data molecules. We demonstrate our method for the Gambler’s Ruin problem as an instance of the Markov chain process. We analyze the method according to both the stochastic chemical kinetics and the mass-action kinetics model. Additionally, we propose a novel {\em unipolar molecular encoding} approach to compute a certain class of polynomials. In this molecular encoding, each variable is represented using two molecular types: a \mbox{type-0} and a \mbox{type-1}. The value is the ratio of the concentration of type-1 molecules to the sum of the concentrations of \mbox{type-0} and \mbox{type-1} molecules. With the new encoding, CRNs can compute any set of polynomial functions subject only to the limitation that these polynomials can be expressed as linear combinations of Bernstein basis polynomials with positive coefficients less than or equal to 1. The proposed encoding naturally exploits the expansion of a power-form polynomial into a Bernstein polynomial. We present molecular encoders for converting any input in a standard representation to the fractional representation, as well as decoders for converting the computed output from the fractional to a standard representation. Lastly, we expand the unipolar molecular encoding for bipolar molecular encoding and propose simple molecular circuits that can compute multiplication and scaled addition. Using these circuits, we design molecular circuits to compute more complex mathematical functions such as $e^{-x}$, $\sin (x)$, and sigmoid$(x)$. According to this approach, we implement a molecular perceptron as a simple artificial neural network.