Browsing by Subject "DC-DC converter"

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    High efficiency, low cost, fully integrated DC-DC converter solution
    (2013-04) Kudva, Sudhir S.
    Rapid advances in the field of integrated circuit design has been advantageous from point of view of cost and miniaturization. However, power dissipation in highly inte- grated digital systems has become a major cause of concern. One of the methods to reduce power dissipation is to dynamically vary the supply voltage (DVS) of digital block depending on the load conditions. This requires high efficiency power converters to dynamically vary the supply voltage. Taking this a step further, the digital system can be further sub-divided into multiple independent voltage domains and DVS applied independently to these voltage domains. To economically support such an implementa- tion fully integrated on-chip power converters are a way forward. This thesis focuses on the design of fully integrated power converters to support DVS type applications. A switched inductive type converter is highly efficient as its efficiency depends only on the parasitics. But, a fully integrated switched inductive converter has some drawbacks and fails to support wide output power range. To circumvent the problem, we have implemented a switched inductive converter that operates in different modes based on the load that the converter supports. In these modes of operation, either the power switch size is scaled or the frequency is scaled to cut down the losses in the converter. The design achieves a peak efficiency of 74.5% and supplies a 450x output power range (0.6mW to 266mW). A fully integrated capacitive converter with all digital ripple mitigation aimed at supporting the lower output power ranges has been designed. The capacitive converter uses a dual loop control, where a single bound hysteretic control loop achieves regulation and the secondary loop achieves ripple control by modulating capacitance size and charge/discharge time of the capacitance used to transfer charge from the input to output. The partial charge/discharge technique used to achieve ripple control does not degrade the efficiency, has been proved both theoretically and experimentally. The design taped out in IBM 130nm process achieves a maximum efficiency of 70% and reduces the measured ripple from 98mV to 30mV at 0.3V and 4mA load current. A test-chip designed to study the impact of placing digital circuits underneath inductor used in power converter type applications is presented. The experimental results show the feasibility of implementing digital circuits underneath the inductor, thereby achieving higher area efficiency for the converter. Finally, a combined induc- tive/capacitive converter where the inductive converter supports the higher power range and capacitive converter supports the lower power ranges is described. The combined converter taped out in IBM 32nm SOI process achieves a maximum efficiency of 85.5% and a power density of 0.7W/mm2. Additionally, we have also proposed a passive resonance reduction technique to re- duce resonance on the supply line in bondwire based packages. The technique utilizes the area underneath the bondpad to implement passives required for resonance reduc- tion.
  • Thumbnail Image
    Item
    Interconnect design techniques for multicore and 3D Integrated circuits.
    (2012-08) Zhou, Pingqiang
    Over the past 40 years, the semiconductor industry has witnessed the exponential growth trend in system complexity as predicted by Moore’s law, facilitated by continuously shrinking transistor and wire dimensions. Three dimensional (3D) circuit technology, with multiple tiers of active devices stacked above each other, is a key approach to achieve increasing levels of integration and performance in the future. Concomitant with exponentially reducing device dimensions, designers face new challenges in maximizing computation while remaining with a stringent power envelope. Over the last decade, multicore processors have emerged as a potential solution to address some of these problems by integrating multiple smaller and more energy efficient cores in order to replace a single, larger core. These cores must communicate through an efficient onchip interconnection network, by ideas such as networks-on-chips (NoCs), and NoC design is vital to both performance and power. This thesis presents solutions to the challenges in on-chip interconnect, more specifically, the on-chip communication and power delivery network of 3D and multicore chips. The first part of this thesis focuses on developing techniques for designing efficient and high-performance NoC architecture for 3D and multicore chips. Depending on the nature of the application, the multicore system may be either a System-on-Chip (SoC), which executes a relatively well-characterized workload, or a Chip multiprocessor (CMP), which is a general purpose processor that should be capable of handling a variety of workloads. For SoCs, this thesis presents an efficient algorithm to synthesize application-specific NoC architectures in a 3D environment. We demonstrate that this method finds greatly improved solutions compared to a baseline algorithm reflecting prior work. We also study the impact of various factors on the network performance in 3D NoCs, including the through-silicon via (TSV) count and the number of 3D tiers. For CMPs, we observe that voltage and frequency scaling (VFS) for NoC can potentially reduce energy consumption, but the associated increase in latency and degradation in throughput limits its deployment. Therefore, we propose flexible-pipeline routers that reconfigure pipeline stages upon VFS, so that latency through such routers remains constant. With minimal hardware overhead, the deployment of such routers allows us to reduce network frequency and save network energy, without significant performance degradation. The second part of this thesis is concerned with the design and optimization of power delivery network for 3D and multicore chips. First, we propose a novel paradigm where we exploit a new type of capacitor, the metal-insulator-metal (MIM) capacitor, together with the traditional CMOS decaps, to optimize the power supply noise in 3D chips. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only. Second, we explore the design and optimization of on-chip switched-capacitor (SC) DCDC converters for multicore processors. On one hand, with an accurate power grid simulator, we find that distributed design of SC converters can reduce the IR drop significantly compared to the lumped design, with improved supply voltage. On the other hand, the efficiency of the power delivery system using SC converters is a major concern, but this has not been addressed at the system level in prior research. We develop models for the efficiency of such a system as a function of size and layout of the SC converters, and propose an approach to minimize power loss by optimizing the size and layout of the SC converters . The efficiency of these techniques is demonstrated on both homogenous and heterogenous multicore chips.