Browsing by Subject "Circuit"
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Item Circuit techniques for cognitive radio receiver front-ends(2012-06) Sadhu, BodhisatwaThis thesis discusses the design of the receiver front-end for software defined radio (SDR) based cognitive radio applications. Two aspects of SDRs for cognitive radios are distinguished: signaling and spectrum sensing. Narrowband wide tuning signaling architectures and instantaneous wideband spectrum sensing architectures are identified as candidates for feasible SDR implementations. Several architectures and circuit im- plementations are reviewed. Wide tuning range, low phase noise frequency synthesizers for signaling, and RF samplers and signal processors for spectrum sensing are identified as critical circuit design blocks.A number of voltage controlled oscillator (VCO) techniques for wide-tuning range, and low phase noise frequency synthesis techniques are developed. Wide-tuning range techniques based on switched inductors are proposed as a way to design inductor- capacitor (LC) VCOs with wide-tuning ranges that maintain a good phase noise and power dissipation performance over the entire tuning range. Switched inductor VCOs are analyzed in detail, and a design framework is developed. Optimized capacitor array design techniques for wide-tuning ranges are discussed. Based on these techniques, mea- surements from two prototype designs are presented, that achieve tuning ranges of 87% and 157% in measurement. They also maintain good phase noise, power consumption, and figure of merit (FOM) over the entire tuning range.In addition, a new family of VCOs that achieve superior phase noise is introduced. This set of novel topologies are based on linearized transconductance using capacitive feedback techniques. They achieve higher amplitudes of oscillation, and consequently, a superior phase noise performance. A wide tuning range is also maintained. The VCOs are analyzed, and detailed measurement results from a design prototype are presented. For spectrum sensing, the design of CRAFT (Charge Re-use Analog Fourier Trans- form): an RF front-end channelizer for software defined radios (SDR) based on a 16 point analog domain FFT is described. The design relies on charge re-use to achieve 47dB average output SNDR on a 5GS/s input, and consumes only 12.2pJ/conv. These numbers represent orders of magnitude improvement on the work reported previously in literature. The thesis also briefly discusses the modeling of circuit non-idealities in CRAFT, and outlines circuit techniques for mitigating these. These design principles enable this implementation to achieve a large dynamic range even at high speeds. Ad- ditionally, these techniques can be easily extended to improve the performance of other passive switched capacitor designs.Item NMDA receptors underlie stress-induced dynamic changes in prefrontal cortical networks: plasticity and function.(2011-01) Parent, Marc-Alexander L.T.The prefrontal cortex (PFC) is a region in the frontal lobe of the cerebral cortex necessary for the proper execution of cognitive behaviors such as attention, memory, and the ordering of actions to accomplish a task. In rodents, lesions of the medial prefrontal cortex (mPFC) impact visiospatial working-memory (vsWM) functions. Neurons in the cerebral cortex are typically silent in alert animals but can become persistently active when brain networks engage them to participate in computations necessary to accomplish a task. During vsWM tasks, neurons in mPFC become persistently active for the delay period of a WM task. The persistent activation of neurons in mPFC by local networks during the delay period of a working memory task in vivo has been suggested to represent a basic neural substrate for maintenance of an internal representation. Stress can alter the performance of animals attempting working memory tasks, and its effects are dynamic over the span of days following a single exposure. Immediately following stress, vsWM is negatively affected and performance on a vsWM task is hindered, while four to twenty-four hours following exposure to stress, vsWM is enhanced. It has been hypothesized that plasticity in local mPFC glutamatergic networks in vivo, driven by stress-response mediators, alters AMPA- and NMDA-mediated neurotransmission as a function of the number of stress exposures and that this plasticity affects persistent, network-driven activity. A previous study has shown that both AMPA- and NMDA-mediated neurotransmission are upregulated twenty-four hours after exposure to mild FS stress (Yuen et al., 2009). The following doctoral thesis supports this conclusion and extends this work to quantify the effects of multiple stress exposures, over several days, on mPFC plasticity and describes a correlation between enhanced glutamatergic synaptic drive and changes in persistent activity. In animals exposed to multiple days of ten-minute, forced-swim stress, NMDA-mediated glutamatergic neurotransmission was upregulated relative to unstressed, naïve animals while AMPA-mediated neurotransmission and intrinsic cellular phenomena remained unaffected. Close examination of isolated NMDA currents from neurons in three-day stressed mice revealed a decrease in the decay rate of these currents relative to naive animals. This augmentation of NMDA-ergic tone yields greater charge entry that could potentially increase the impact of synaptic drive on neuronal activity as well as enhance synaptic integration. The upregulation of NMDA-mediated neurotransmission in three-day stressed animals was found to occur via the upregulation of the NR2B subunits at synaptic NMDA receptors. Together, a decrease in NMDA current decay rate via inclusion of NR2B subunits and the lack of evidence for stress-induced AMPA current modulation resulted in an increase in NMDA-to-AMPA ratio (NAR) at synaptic mPFC networks. These observed changes in glutamatergic neurotransmission, after a single or multiple exposures to forced swim, are paralleled by changes in persistent activity. Individual PA events were recorded from naïve, one-day and three-day stressed mice. PA events recorded from both stressed groups were increased in duration relative to naïve animals. These data support the conclusion that stress regulates glutamatergic neurotransmission in the mPFC, affecting the ability of neurons to remain persistently active.Item Piezoelectric energy harvesting utilizing human locomotion.(2010-07) Wang, GuojunPrevious studies have shown that not only are piezoelectric materials feasible for energy harvesting, they are feasible as an energy harnessing medium in shoes during walking. Continuing in that vein, this thesis provides new designs to better apply mechanical stress and achieve higher power output. Two points of stress during walking were used for energy harvesting. 1.) The heel of the shoe, for when a person’s foot first lands on the ground during the initial stage of the step. 2.) The ball of the shoe, for the curling motioning of the foot as the person propels forward finishing a step. A flexible, multilayered insole was developed for the ball of the shoe operation and integration into the sole of a specially selected “street shoes”. The insole consists of six layers of PVDF sheets, three sheets per side, adhered to a thick but flexible Nylon core. The PVDF absorbs the mechanical compression or tension stress, depending on the side they are on, thereby creating a charge differential across the surface of each sheet. A rigid, reversed clamshell piezoceramic transducer was developed and integrated into the heel of the same shoe. The insert consists of two Thunder PZT unimorph connected in parallel and mounted inside a steel housing to facilitate optimal force transference. The inherent capacitive property of the piezoelectric materials and its very low frequency of operation (~ 1Hz or 1 step per second), allows for very little current to be extracted through conventional full-wave rectifier harvesting circuit. Due to previous research success with resonating an inductor in series with the piezoelectric source, an energy harvesting circuit coined “Synchronized Switch Harvesting on Inductor” SSHI was utilized to increase power output. However, due to the inability to correctly synchronize the switching circuit and lack of proper piezoelectric source modeling, SSHI circuit only provided marginal improvement in power output ~10-20% as oppose to previous study demonstrating 250%+ output. Nevertheless, by using only full-wave rectifier harvesting circuits, the new PVDF insole and PZT insert designs have propelled harvestable energy to 11-13mW from one shoe, with a combined generation of 22-26mW for both shoes.Item Spin-Based Logic and Memory Technologies for Low-Power Systems(2016-02) Kim, JongyeonAs the end draws near for Moore’s law, the search for low-power alternatives to CMOS technology is intensifying. Among the various post-CMOS candidates, spintronic devices have gained special attention due to its unique features such as zero static power, compact size, and instant wakeup, while enabling an entirely new class of architectures such as processor-in-memory, logic-in-memory, and neuromorphic computing. However, traditional spintronics research has been mainly limited to the materials and single device level, so the main aim of this dissertation is to clearly describe spin-based logic and memory technologies by exploring the trade-off points across different levels of design abstraction (i.e. device, circuit, and architecture). For spin-based logic, we benchmark the system-level capability of spin-logic technology using a hypothetical spintronic-based Intel Core i7 as a test vehicle. We describe how spin-based components are integrated into a computing system and the advantages that result. Even with early promises such as zero static power, lower device count, and lower supply voltage, technical barriers associated with spin devices such as low spin injection, limited spin diffusion length, and intrinsically high activity factor result in higher active power than CMOS. For spin-based memory, a key aspect of technology evaluation is the development of a reliable MTJ model, so we first propose a technology-agnostic MTJ model specifically designed for evaluating the scalability and variability of STT-MRAM circuits. Using the proposed model, we evaluate the circuit-level scalability of MTJ technologies providing the detailed scaling methods and projection scenarios down to 7nm. For use in high speed on-chip cache applications, we also explore the feasibility of non-traditional MRAMs such as spin-Hall effect (SHE) MRAM which provides superior switching efficiency. In addition to the spintronics research, a logic-compatible eflash-based neuromorphic core is designed to provide a highly efficient architecture for neural computing. We use a logic-compatible embedded flash memory to store synaptic weights to provide a simple implementation of restricted Boltzmann machine (RBM) which is a well-known neural algorithm for digit recognition. With the proposed current-based architecture, a neuron operation can be accomplished by simply comparing two currents corresponding to excitatory and inhibitory weights without large digital neuron circuits used in previous works.