Browsing by Subject "CMOS"

Now showing 1 - 5 of 5
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    Circuit techniques for cognitive radio receiver front-ends
    (2012-06) Sadhu, Bodhisatwa
    This thesis discusses the design of the receiver front-end for software defined radio (SDR) based cognitive radio applications. Two aspects of SDRs for cognitive radios are distinguished: signaling and spectrum sensing. Narrowband wide tuning signaling architectures and instantaneous wideband spectrum sensing architectures are identified as candidates for feasible SDR implementations. Several architectures and circuit im- plementations are reviewed. Wide tuning range, low phase noise frequency synthesizers for signaling, and RF samplers and signal processors for spectrum sensing are identified as critical circuit design blocks.A number of voltage controlled oscillator (VCO) techniques for wide-tuning range, and low phase noise frequency synthesis techniques are developed. Wide-tuning range techniques based on switched inductors are proposed as a way to design inductor- capacitor (LC) VCOs with wide-tuning ranges that maintain a good phase noise and power dissipation performance over the entire tuning range. Switched inductor VCOs are analyzed in detail, and a design framework is developed. Optimized capacitor array design techniques for wide-tuning ranges are discussed. Based on these techniques, mea- surements from two prototype designs are presented, that achieve tuning ranges of 87% and 157% in measurement. They also maintain good phase noise, power consumption, and figure of merit (FOM) over the entire tuning range.In addition, a new family of VCOs that achieve superior phase noise is introduced. This set of novel topologies are based on linearized transconductance using capacitive feedback techniques. They achieve higher amplitudes of oscillation, and consequently, a superior phase noise performance. A wide tuning range is also maintained. The VCOs are analyzed, and detailed measurement results from a design prototype are presented. For spectrum sensing, the design of CRAFT (Charge Re-use Analog Fourier Trans- form): an RF front-end channelizer for software defined radios (SDR) based on a 16 point analog domain FFT is described. The design relies on charge re-use to achieve 47dB average output SNDR on a 5GS/s input, and consumes only 12.2pJ/conv. These numbers represent orders of magnitude improvement on the work reported previously in literature. The thesis also briefly discusses the modeling of circuit non-idealities in CRAFT, and outlines circuit techniques for mitigating these. These design principles enable this implementation to achieve a large dynamic range even at high speeds. Ad- ditionally, these techniques can be easily extended to improve the performance of other passive switched capacitor designs.
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    CMOS circuits for multi-antenna communication systems.
    (2010-09) Patnaik, Satwik
    Multi-antenna systems allow for higher communication rates without substantial increase in hardware and power. This has led to significant interest in incorporating multi-antenna communication into upcoming wireless standards, like the 802.11n. This thesis focuses on CMOS circuits and architectures for multi-antenna wireless communication systems. Specifically, we will propose solutions for a special class of multi-antenna systems called phased-array systems. The most important circuit block in a phased-array system is the phase-shifter. Traditional phased-array systems, mostly military radars, used external ferrite phase-shifters for microwave applications, which were wide-band, almost noiseless, highly linear and had high power-handling capability, but were bulky. Commercial wireless systems rely on portability and low-power, with the result that CMOS is the technology of choice and most products are fully integrated on a single-chip. On-chip CMOS phase-shifters have not been able to match the performance of ferrite phase-shifters. Consequently, CMOS-based phased-array systems have relied on a modified architecture known as the LO-phase shifting architecture to deliver comparable performance. In this work, we first present two novel schemes for the phase-generation network for the LO-phase-shifting architecture, based on a phenomenon called injection-locking. The injection-locked oscillator (ILO) is used as a phase-shifter. The two schemes are integrated into a dual-mode architecture for a phased-array receiver providing us with the advantages of both. The prototype, operating at 2.4-GHz, is fabricated in a 0.13-μm CMOS technology. It requires lower power and area compared to previous state-of-the-art designs. Measurement results from this prototype show excellent agreement with the theoretical performance predicted for the phased-array receiver. Both architectures have also been extended to two-dimensional phased-array systems. A majority of the commercial phased-array applications are focused on the mm-wave regime. We have verified that our architecture can operate at these frequencies as well. A 24-GHz two-channel CMOS phased-array receiver has been designed and fabricated in 0.13-μm BiCMOS technology. In this architecture, the injection-locked oscillator not only acts as a phase-shifter and buffer, but also as a frequency tripler. Because of this multi-functionality of the ILO, the overall area and power of this receiver are better than other state-of-the-art designs. Since the LO distribution network now operates at one-third the LO frequency, it allows for further power savings in the distribution network. Finally, a beam-forming receiver based on the Fast-Fourier Transform (FFT) is presented. In this architecture, the beam-forming operations are performed in the baseband processing section. Owing to a low-power FFT architecture and the inherent properties of the FFT, multiple beams can be created at closely-spaced frequencies. This allows the use of narrow-band transmitter and receiver architectures for the RF section. A two-channel receiver based on this architecture has been designed in a 65-nm CMOS process. In addition, to these different receiver architectures, a novel 24-GHz UWB-LNA is presented. The LNA, which has been integrated as part of a UWB receiver, is presented in this thesis. However, the overall UWB receiver design is not presented here.
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    Fast hopping frequency synthesis techniques using injection locking.
    (2010-03) Lanka, Narasimha
    The use of fast-hopping frequency synthesis is a critical component of frequency-hopped spread spectrum (FHSS) systems. FHSS offers many advantages including high resistance to narrow-band interference, low probability of intercept and capability to share spectrum with other narrow-band systems. Such qualities make FHSS a particularly attractive scheme for military applications. In commercial applications, the WiMedia specification for ultra-wideband (UWB)/Wireless-USB presents another standard that uses fast frequency-hopping. The most stringent constraint on the frequency synthesizer in these systems is the band-switching time. This thesis presents novel techniques for fast-hopping frequency synthesis based on injection locking. First, extensive study of the transient behavior of oscillators under injection is presented. Analystical expressions are used as the basis for the study and interesting aspects of the locking process of an injection-locked oscillator (ILO) are identified. Two techniques, lock-range dependent fast-locking and predictive fast-locking, are then presented. In the first technique, fast locking times are achieved by using large lock-ranges for the ILO. Phase dependence of lock-time is exploited in the second technique and extremely fast settling is achieved. These theoretical findings are verified through simulation and measurements from a multiple of oscillator prototypes. Measurements from a low-speed Colpitts oscillator running at 57 MHz are used to verify tracking, out-of-lock behavior and frequency settling of ILOs. Measurements from an LC-oscillator implemented in 0.13-um CMOS technology operating at a free-running frequency of 3.4 GHz are used to verify the dependence of locking time on the lock range and the initial phase of injection. Novel architectures for fast frequency-hopping synthesizers and high frequency direct-digital synthesizer are then presented. Finally, a complete prototype for WiMedia-UWB/Wireless-USB-compliant fast-hopping frequency synthesizer architecture with quadrature outputs, based on sub-harmonic injection-locking, is presented. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator is derived. The overall design is a CMOS-only implementation and has been fabricated in 0.13-um SiGe BiCMOS process. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5 deg. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst-case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer reported to-date.
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    Implementation of on-chip thermal sensor using off-leakage current of a transistor
    (2010-01) Dalal, Hussain Firoz
    Abstract summary not available
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    Ultra Fast Frequency Hopping Transceiver Design and Implementation for Secure Wireless Communication
    (2019-09) Mousavi, Seyednaser
    Frequency hopping spread spectrum (FHSS) is used in a completely new way to pro- vide processing gain for the rst time.To improve the in-band blocker handling capability of the receiver the processing gain is realized in RF domain. The RF transceiver system is designed to provide 20dB of processing gain before any amplication occurs in receiver chain. This enables the receiver to reduce any in-band blocker by 20dB before the LNA and provide self-interference cancelation for the local transmitter that is located on the same chip. This enhances the dynamic range of the receiver above what has been possi- ble before. Since this is the rst attempt to build such a system, no system level analysis existed prior to this work. So on top of IC design, system level design and modeling of the system is presented as well. Two major circuits were developed before this system was feasible. First, an ultra- fast front-end band-pass lter was designed to perform the correlation function. This circuit needs to switch frequency in extremely short periods of time, i.e. 20ns. Secondly, since the correlator circuit hopping speed depends on a fast-hopping LO signal, a signal generator sub-system was developed to generate the LO o a constant frequency RF signal. This sub-system consists of a digital oscilator, DAC, and an injection locked oscillator (ILO) that is used as a high-Q band-pass lter that can in theory switch frequency instantaneously. The digital nature of the LO generation circuits and the ILO's ability to move fast in frequency domain enables the sub-system to generate ultra- fast hopping LO signals. The system is designed to accommodate 470Kbps in various wireless channel environ- ments while providing 20dB of processing gain. This translates into 50 Mhop/s frequency hopping speed that is more than 300 times faster than the state of the art. The RF met- rics of developed components and system level performance are proven in silicon and measurements are reported. The results are presented here and in top conferences and journal papers.