Browsing by Subject "Bias temperature instability"

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    Circuit-Based Reliability Characterization Methods in Advanced CMOS Technologies
    (2014-01) Wang, Xiaofei
    Integrated circuit reliability has become an increasingly important design consideration as the CMOS technology keeps aggressively scaling to its physical limit. The parametric shifts and circuit failures caused by reliability issues such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and Electromigration (EM) have become more prevalent as electrical fields and current density continue to increase in scaled devices. In addition, the rapid introduction of process improvements, such as high-k/metal gate stacks, has led to new reliability issues including positive BTI (PBTI) in n-type transistors. Traditionally, designers deal with reliability problems by adding a conservative design guardband calculated by aging models based on the worst-case degradation scenario. However, there are a few issues associated with this method: 1. the power and performance overhead of guardbanding have started to increase in the newer technologies. 2. the aging models used by designers to are mostly based on the device probing data, which is not accurate to predict the circuit performance degradation. 3. the device probing has the drawbacks of expensive costs of probing equipment and limited timing resolution. In order to resolve these issues, one of the key aspects is to develop accurate and efficient means to measure the effects of different aging mechanisms on circuit parameters accurately. For this purpose, several unique on-chip circuit-based sensing systems have been proposed, which provide us with important advantages: namely, pico-second timing resolution for usage condition stress, micro-second measurement interruption to prevent unwanted recovery, and excellent immunity to voltage and temperature drifts. The proposed odometer designs utilize standard logic gates and a simple scan-based interface, making them suitable for integrating into an actual processor system. In this thesis, four dedicated on-chip circuit designs that we have implemented over two generation of process technology to characterize reliability issues on various types of circuits will be presented.