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Browsing by Subject "ADC"

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    High speed analog-to-digital conversion utilizing time quantization.
    (2010-02) Orser, Heather
    As communication speeds have increased, high speed and resolution analog-to-digital converters (ADCs) have become necessary. ADCs have traditionally relied on comparing an input voltage to a reference voltage and digitizing the result. The increased speed of operation requires faster processes, which in turn limit the usable input voltage range due to breakdown voltage limitations. The work presented in this thesis studies two aspects of ADCs and possible alternate implementations to address existing limitations. A sample-and-hold amplifier (SHA) is a common first stage for ADCs. At high frequencies, the SHA provides valuable timing relief to subsequent stages. Biasing of the high speed circuits consumes valuable headroom in low voltage circuits, limiting operation of existing architectures to supply voltages of at least 1.8V. An alternative architecture is presented that allows reduced supply voltages to be used. An alternative core ADC architecture is also discussed. The implementation chosen utilizes a time measurement system that quantizes time instead of voltage. A phase delay proportional to the input voltage is first generated. This signal is then quantized using a time-to-digital converter. The use of active devices in the clock path is eliminated, allowing for increase operation speed while delay generation is accomplished with varactors, allowing for large voltage swings on the input signal.
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    Jitter Suppression Techniques for High Speed Communication Systems
    (2019-12) Jamalizavareh, Shiva
    The drive towards fast and robust communication has resulted in an increased focus on high frequency analog and digital transceivers. One of the major challenges in high-speed analog transceivers, is the front-end analog-to-digital converter (ADC). All ADCs rely on periodic samples of the input signal. To enable high accuracy analog to digital conversion at high frequencies, a clean sampling clock is required. However, the non-idealities in the clock generation and distribution system can result in uncertainties in the sampling edges of the clock signal. These uncertainties are referred to as jitter. In many cases, the jitter requirement on the sampling clock is less than 100 fs, rms, realizing which is not trivial. More important, there exists a disconnect between the clock designers and the ADC designers, when it comes to jitter suppression. While clock designers are focused on minimizing the narrow-band clock jitter, the ADC designers have to deal with the broadband noise in the clock path, which is detrimental to the ADC's performance. The question we try to answer in this thesis is, whether rather than tackling the jitter at the source, one can reduce the jitter sensitivity of the ADCs by using jitter-resilient sampling techniques. A review of various sources of jitter, and the impact of jitter on analog and digital transceivers is presented. This facilitates the understanding, characterizing, and ultimately reducing the jitter-induced errors in the communication systems. A new sampling technique, called Delta Sigma sampling, is proposed to suppress the jitter induced sampling error in ADCs. The design uses a Delta Sigma architecture with low oversampling ratio (OSR) to shape the jitter error, in the same way that a Delta Sigma ADC shapes the quantization error. The Delta Sigma sampler, however, does not have a quantizer, and as a result, the output of the sampler is a sampled-and-held signal. Therefore, a Delta Sigma sampler can be used as a jitter-resilient front-end for any type of ADC. To prove the functionality of the proposed sampling technique, a comprehensive time-domain analysis is presented. In this analysis, 1st-, 2nd-, and higher order Delta Sigma samplers with various feedback architectures are considered. The feedback architectures include return-to-zero (RZ), non return-to-zero (NRZ), and switched-capacitor. Three sources of jitter are identified in the sampler: the sampling clock jitter, the feedback pulse edge jitter, and the feedback pulsewidth variations. We show that first, the switched-capacitor feedback impairs the jitter shaping properties of the loop. In fact, the decaying nature of the pulse reduces the loop order to N-1. Second, a 1st-order Delta Sigma sampler has the same signal-to-jitter noise ratio (SJNR) with switched-capacitor feedback, and with constant-pulsewidth RZ feedback. RZ feedback relaxes the slew rate requirements of the integrator, thereby reducing the power consumption of the system. However, the feedback pulsewidth variations degrade the SJNR significantly. A new clocking scheme, called correlated clocking, is introduced to alleviate the pulsewidth jitter of the RZ feedback. This technique uses the correlation between the rising and falling edges of the feedback clock to minimize the feedback pulsewidth variations. The proposed clocking technique can also be used in continuous-time Delta Sigma ADCs. The analysis indicates that the maximum SJNR benefit of a Delta Sigma sampler over a Nyquist sampler is equal to 10*log10(OSR)+4.77 dB. That is equivalent to a 4X reduction of clock jitter in a Nyquist sampler or 3X increase in OSR for an oversampler. The maximum SJNR is independent of the loop order and the feedback architecture, and it stays constant for OSR >5. Finally, we show that in contrary to the common belief, the feedback edge jitter dominates the overall jitter in the 2nd- and higher-order samplers, as it translates into feedback pulsewidth variations at the output of the second integrator. This error gets 1st-order shaped, regardless of the loop order, making it the dominant source of jitter in higher order Delta Sigma loops. The theoretical analysis is veried by numerical simulations in MATLAB and behavioral simulations in Cadence. In addition, a 5 GS/s 1st-order Delta Sigma sampler with correlated clocking is implemented in 65 nm CMOS technology, and verified through circuit-level simulations in Cadence.