Browsing by Author "Zhou, Chen"

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    Characterization of Integrated Circuit Reliability and Security Using On-Chip Monitoring Circuits
    (2018-07) Zhou, Chen
    This thesis has thoroughly summarized my six years of PhD research works in Electrical and Computer Engineering department, University of Minnesota. The novelty and contribution of my works is the evaluation of reliability and security on silicon chips using on-chip based approach. As has been fully explained in this thesis, on-chip based approach has several advantages: 1) high speed due to locally generated clock and data signals; 2) less test time from parallel operation; 3) low cost and flexible with fully custom controlled on-chip logic. Our EM works benefit a lot from the on-chip heater design. It has been proved to be very effective and robust for long time high temperature stress study. Temperature control requires dedicated power adjustment, which still has the room to be improved. Similar to previous published work, we found almost no failure effect under AC stress current. In order to study any potential weak effect of AC stress current, more test structure and approach are introduced in the 16nm FinFET tape-out. Unlike the low possibility in AC EM failure, failures on IC power grid have higher possibility and are more difficult to detect and characterize. The voltage tapping method adopted in our test chip has provided us great insight into the power grid EM failure. Our 16nm test chip includes more realistic power grid structure, which will help us to get better understanding in real chip EM failure. The hot carrier injection test work clearly indicated the saturation current variation shrinking phenomena resulting from self-heating induced temperature variation. Under DC stress condition, device with lower initial threshold voltage can conduct a higher current, associated with a higher temperature. Since HCI aging speed is positively related to temperature. Low threshold voltage devices end up with larger degradation, thus the saturation current variation is reduced. It is a good news for circuit design. However, the limitation of traditional DC stress mode need to be considered. To mimic the real chip operation, AC stress mode or pulsed current stress mode should be used instead of DC stress. Therefore, the self-heating induced temperature variation will be suppressed. Will we still see the same variation shrink phenomena under AC or pulsed current stress mode? This question may be answered in future work in this research community. Physical unclonable function is a promising silicon chip application due to the security requirement of Internet of Things (IoT) devices. PUF is a low cost solution for the security of IoT devices due to its compatibility of logic semiconductor process. Of the four metrics to evaluate the PUF design, uniqueness and randomness are usually easy to meet when symmetric layout is adopted. On the other hand, stability and security are much harder. The natural noise inside silicon devices and the condition variation can easily flip the responses which are weak biased originally. Modern modeling attach techniques are so powerful to compromise even the non-linear PUF systems. In my work, the on-chip sampling circuits help collect the real silicon data. A XOR based PUF system, together with the linear model based challenge selection scheme was proposed in my work to achieve both perfect stability and solid security. Although at the time when I graduate, the PUF circuits haven't been widely adopted by the industry, I hope its time will come in the future once the era of IoT devices arrives.