Browsing by Author "Ayinala, Manohar"

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    High Throughput VLSI Architectures for CRC/BCH Encoders and FFT computations
    (2010-12) Ayinala, Manohar
    Linear feedback shift register (LFSR) is an important component of the cyclic redun- dancy check (CRC) operations and BCH encoders. This thesis presents a mathematical proof of existence of a linear transformation to transform LFSR circuits into equivalent state space formulations. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all irreducible polynomials used in CRC operations and BCH encoders. A new formu- lation is proposed to modify the LFSR into the form of an IIR ¯lter. We propose a novel high speed parallel LFSR architecture based on parallel In¯nite Impulse Response (IIR) ¯lter design, pipelining and retiming algorithms. The advantage of proposed approach over the previous architectures is that it has both feedforward and feedback paths. We further propose to apply combined parallel and pipelining techniques to eliminate the fanout e®ect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. A comparison between the proposed and previous architectures shows that the proposed parallel architecture achieves the same critical path as that of previous designs with a reduced hardware cost. Further, this thesis presents a novel approach to develop the pipelined architectures for the fast Fourier transform (FFT). A formal procedure for designing FFT architec- tures using folding transformation and register minimization techniques is proposed. Novel parallel-pipelined architectures for the computation of fast Fourier transform are derived. The proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. A comparison is drawn be- tween the proposed designs and the previous architectures. The power consumption can be reduced up to 37% and 50% in 2-parallel FFT architectures. The output samples are obtained in a scrambled order in the proposed architectures. Circuits to reorder these scrambled sequences to desired order are presented.
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    Low-power architectures for signal processing and classification systems.
    (2012-07) Ayinala, Manohar
    Digital signal processing and classification algorithms play a crucial role in modern day biomedical monitoring systems. Fortunately, emerging sensors and stimulators as well as specialized networking technologies have enabled biomedical devices to advance to new frontiers. Deep-brain stimulators, for instance, offer unprecedented modalities for delivering therapy to patients affected by neurological conditions, ranging from Parkinson’s disease to epilepsy; out-patient monitoring networks raise the possibility of comprehensive yet cost-scalable healthcare delivery over large populations with increasingly diverse disease states. The central need, as these systems advance towards intelligent, closed-loop operation, is the ability to detect specific physiological states of interest from signals that are available through sensors. A key challenge in closed-loop biomedical systems is the ability to detect complex physiological states from the patient data within a constrained power budget. Signal processing and data-driven machine learning techniques are major enablers for modeling and detection of such states. However, the computational power scales with the complexity of models required. This thesis considers the VLSI implementation of basic signal processing techniques such as fast Fourier transform (FFT), power spectral density (PSD) computation. Reconfigurable architectures for classification algorithms including support vector machines (SVM) and Adaboost are also presented. The proposed architectures improve performance and reduce area/power consumption. First, we present a novel methodology to design parallel pipelined FFT architectures using folding transformation and register minimization techniques. Novel parallelpipelined architectures for the computation of complex valued fast Fourier transform are derived. The proposed architectures overcome prior bottlenecks and achieve full hardware utilization. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. This significantly reduces power at same speed or increases speed at same power consumption level. The power consumption can be reduced up to 37% in 2-parallel architectures. Further, we propose a novel approach to develop pipelined fast Fourier transform (FFT) architectures for realvalued signals. Novel 2-parallel and 4-parallel architectures are presented for radix-23 and radix-24 algorithms. The proposed radix-23 and radix-24 architectures lead to low hardware complexity compared to a prior RFFT architecture. We propose an efficient architecture for memory-based in-place FFT/IFFT computation. A conflict-free memory addressing scheme is proposed to ensure the continuous operation of the FFT processor. The proposed architecture requires fewer computation cycles along with the low hardware cost compared to prior work. We then present a low-complexity algorithm and architecture to compute power spectral density (PSD) using the Welch method. The complexity reduction comes at the cost of slight performance loss in accuracy due to the approximation used for the implementation of the fractional delay filter. The performance loss is 6-8% using fractional delay filter with 2-3 multipliers. A novel architecture is presented based on the proposed algorithm which consumes 33% less energy compared to the original method. We propose a low-energy reconfigurable architecture for support vector machines (SVMs) based on approximate computing by exploiting the inherent error resilience in the computation. We present two design optimizations, fixed-width multiply-add and non-uniform look-up table (LUT) for exponent function to minimize power consumption and hardware complexity while retaining the classification performance. The proposed design consumes 31% less energy on average compared to a conventional design. Finally, we present a novel low-complexity patient-specific algorithm for seizure prediction using spectral power features. The proposed algorithm achieves a sensitivity of 94.375% for a total of 71 seizure events with a low false alarm rate of 0.13 per hour and 6.5% of time spent in false alarms using an average of 5 features for the Freiburg database. The low computational complexity of the proposed algorithm makes it suitable for an implantable device.