Design of a fourth-order continuous-time delta-sigma A/D modulator with clock jitter correction.

Abstract

In recent years, there has been growing interest in both industry and academia to use delta-sigma A/D converters for wideband wireless communication applications. Continuous-time (CT) delta-sigma modulators (ΔΣM) are of particular importance, mainly due to their advantages in terms of low power consumption, low noise, high speed and inherent anti-aliasing filtering capability. However, they are much more sensitive to clock jitters than their digital-time (DT) counterparts, limiting their practical applications. In this project, we present a CT delta-sigma modulator design that can significantly reduce the clock jitter effects. A top-down methodology is utilized starting from the system-level design, and then followed by circuit-level design. In the system-level design, key design challenges are addressed and various non-ideal effects including clock jitter effects are modeled with MATLAB/SIMULINK to determine the specifications for each building block. In particular, it is shown that a simple fixed-width return-to-zero (RZ) current feedback technique can effectively reduce the SNR loss caused by clock jitters. System-level simulation outputs are then used as input constraints for the circuit-level design, which consists of a 1.5V CT ΔΣM in IBM 0.13μm process compatible for use with the WCDMA technology. The building blocks include operational transconductance amplifiers (OTAs), comparator, return-to-zero logic circuit, digital-to-analog (DAC) current feedback blocks and summing block. Circuit design and layout were completed using Cadence Design Systems software. Simulations show that this ΔΣM circuit has a SNR of 65.5dB for a 0.1V input at 468.75kHz.