Timing Induced Error Analysis for Wallace Tree Multipliers
2015-09
Loading...
View/Download File
Persistent link to this item
Statistics
View StatisticsJournal Title
Journal ISSN
Volume Title
Title
Timing Induced Error Analysis for Wallace Tree Multipliers
Authors
Published Date
2015-09
Publisher
Type
Thesis or Dissertation
Abstract
With the increasing demand for embedded and mobile systems to support wide breadth of applications with tight power budgets as well as increased heat dissipation in processors due to increased operating frequencies and processing capacity per chip with technology scaling, energy efficiency in VLSI systems has become a critical constraint. On the other hand with technology scaling into sub nm, energy efficiency due to scaling is diminished due to increased process variability. Process variations result in delay deviations. Voltage over scaling is considered as an effective technique to reduce energy consumption. Process variability and voltage over scaling result in timing errors. This thesis focuses on understanding the effects of timing error on different multiplier arithmetic units, since multipliers are the one of the key hardware blocks in signal processing systems as well as general purpose processors and consume considerable amount of power. It is observed that different hardware implementations of same multiplier function may respond very differently to timing errors. Hence few architectures are inherently more error resilient to timing errors and selection of appropriate architecture will result in better energy efficiency under voltage over scaling or over clocking. Second part of the thesis presents that same multiplier architecture will have different error statistics for different input distributions. Since most of the real signals used in signal processing systems and communication systems are Gaussian distributed, multiplier architectures are tested for Gaussian inputs and observations show that performance under timing induced error is worse for Gaussian distributed inputs than uniformly distributed inputs.
Keywords
Description
University of Minnesota M.S.E.E. thesis. September 2015. Major: Electrical Engineering. Advisor: Keshab Parhi. 1 computer file (PDF); vii, 46 pages.
Related to
Replaces
License
Series/Report Number
Funding information
Isbn identifier
Doi identifier
Previously Published Citation
Suggested citation
Santhapuram, Vaishnavi. (2015). Timing Induced Error Analysis for Wallace Tree Multipliers. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/175491.
Content distributed via the University Digital Conservancy may be subject to additional license and use restrictions applied by the depositor. By using these files, users agree to the Terms of Use. Materials in the UDC may contain content that is disturbing and/or harmful. For more information, please see our statement on harmful content in digital repositories.