Vinod, Arvind2011-08-312011-08-312011-05https://hdl.handle.net/11299/114308University of Minnesota M.S. thesis. June 2011. Major: Electrical engineering. Advisor:Dr. Chris H. Kim. 1 computer file (PDF); vii, 319 pages, appendices A-C.In this work, the automatic placement and routing tools from Cadence Virtuoso(R)-GXL layout tool suite have been used to create a flow to allow automatic placement and routing of small to medium sized blocks using schematic or verilog gate-level netlist as input, for aiding the design of testchips. The flow has also been tried on a larger design and timing results are compared with results from a commercial P&R tool-Cadence Encounter(R) Digital Implementation System.en-USElectrical engineeringThesis or Dissertation