Patnaik, Satwik2012-11-142012-11-142010-09https://hdl.handle.net/11299/139074University of Minnesota Ph.D. dissertation. September, 2010. Major: Electrical Engineering. Advisor: Prof. Ramesh Harjani. 1 computer file (PDF); xii, 134 pages.Multi-antenna systems allow for higher communication rates without substantial increase in hardware and power. This has led to significant interest in incorporating multi-antenna communication into upcoming wireless standards, like the 802.11n. This thesis focuses on CMOS circuits and architectures for multi-antenna wireless communication systems. Specifically, we will propose solutions for a special class of multi-antenna systems called phased-array systems. The most important circuit block in a phased-array system is the phase-shifter. Traditional phased-array systems, mostly military radars, used external ferrite phase-shifters for microwave applications, which were wide-band, almost noiseless, highly linear and had high power-handling capability, but were bulky. Commercial wireless systems rely on portability and low-power, with the result that CMOS is the technology of choice and most products are fully integrated on a single-chip. On-chip CMOS phase-shifters have not been able to match the performance of ferrite phase-shifters. Consequently, CMOS-based phased-array systems have relied on a modified architecture known as the LO-phase shifting architecture to deliver comparable performance. In this work, we first present two novel schemes for the phase-generation network for the LO-phase-shifting architecture, based on a phenomenon called injection-locking. The injection-locked oscillator (ILO) is used as a phase-shifter. The two schemes are integrated into a dual-mode architecture for a phased-array receiver providing us with the advantages of both. The prototype, operating at 2.4-GHz, is fabricated in a 0.13-μm CMOS technology. It requires lower power and area compared to previous state-of-the-art designs. Measurement results from this prototype show excellent agreement with the theoretical performance predicted for the phased-array receiver. Both architectures have also been extended to two-dimensional phased-array systems. A majority of the commercial phased-array applications are focused on the mm-wave regime. We have verified that our architecture can operate at these frequencies as well. A 24-GHz two-channel CMOS phased-array receiver has been designed and fabricated in 0.13-μm BiCMOS technology. In this architecture, the injection-locked oscillator not only acts as a phase-shifter and buffer, but also as a frequency tripler. Because of this multi-functionality of the ILO, the overall area and power of this receiver are better than other state-of-the-art designs. Since the LO distribution network now operates at one-third the LO frequency, it allows for further power savings in the distribution network. Finally, a beam-forming receiver based on the Fast-Fourier Transform (FFT) is presented. In this architecture, the beam-forming operations are performed in the baseband processing section. Owing to a low-power FFT architecture and the inherent properties of the FFT, multiple beams can be created at closely-spaced frequencies. This allows the use of narrow-band transmitter and receiver architectures for the RF section. A two-channel receiver based on this architecture has been designed in a 65-nm CMOS process. In addition, to these different receiver architectures, a novel 24-GHz UWB-LNA is presented. The LNA, which has been integrated as part of a UWB receiver, is presented in this thesis. However, the overall UWB receiver design is not presented here.en-USBeamformingCMOSInjection-lockingLNAmm-wavePhased-arrayThesis or Dissertation