Saha, Anindya2020-02-262020-02-262017-12https://hdl.handle.net/11299/211792University of Minnesota Ph.D. dissertation. December 2017. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xviii, 129 pages.The voice-only mobile-telephony 1G systems have evolved a long way to today’s data-driven 4G LTE networks, causing an exponential increase in mobile broadband data consumption. Furthermore, 5G is expected to deliver unprecedented data rates (tens of Gbps) exploiting mm-wave bands (30-300 GHz). Analog-to-digital converters (ADC) are one of the crucial factors in determining the pursued data rates. In the first part of this dissertation, a 100MS/s 9-bit companding SAR ADC, which exploits the statistical properties to reduce the PAPR of broadband multi-carrier signals in 4G LTE has been investigated. The architecture provides amplitude-specific gain with a fast instantaneous AGC, reducing the effects of PAPR and optimizing quantization noise, emulating the performance of a higher resolution ADC. Additionally, gain-before-sampling results in reduced sampling capacitor size, which lowers power and area. In the second part of this dissertation, a 1 GS/s 7-bit ADC using PWM technique and time-domain quantization is investigated to harness the benefits of the rapidly improving time resolution, so that the envisioned data rates in 5G can be realized with the lowest possible power. Thanks to digital delay line based time-domain computations, proposed architecture is highly digital therefore scalable, which is beneficial since scaling does not favor voltage-domain circuits.en4G LTE5GCompandingOFDMPWMSAR ADCThesis or Dissertation