Hu, Chia-Lin2015-04-132015-04-132014-08https://hdl.handle.net/11299/171174University of Minnesota Ph.D. dissertation. August 2014. Major: Electrical Engineering. Advisor: Ted K. Higman. 1 computer file (PDF); vi, 68 pages.This research presents on a CMOS sensor, which includes a chopper stabilized front-end amplifier with DC suppressed feedback and a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with background calibration. It could reduce the flicker noise interference in the low frequency and suppressed the DC offset voltage between the two input signals. Therefore, this structure is suitable for bio-medical applications. The bio-medical signals are smaller than 5 mV in the low frequency between 0.01 Hz and 1 kHz. After amplifying, the signals will be digitized by a 12-bit SAR ADC.The chopper stabilized amplifier has a clock rate, 16 kHz, controlling the chopper switches and shifting the original signals to 16 kHz in order to reducing the flicker noise. In our case, the flicker noise could lower at least 80 times at this clock rate. The two-Thomas Biquad low-pass filter, as the anti-aliasing filter, could suppress the harmonic signals at least 40dB before digitalized by ADC. For the 12-bit SAR ADC, the differential nonlinearity (DNL) is +0.576/-0.96 least significant bit (LSB), and the integral nonlinearity (INL) is +0.534/-0.655 LSB. The signal-to-noise and distortion ratio (SNDR) can be estimated 69dB. The effective number of bits (ENOB) is 11.17. The total power dissipation of the ADC is 60-µW at 500-KS/s sampling rate and the supply voltages are ±0.5V. The figure of merit (FOM) is 52.08-fJ/conversion step.enChopper stabilizationFlicker noiseSAR ADCElectrical engineeringThesis or Dissertation