Liang, Zhaoxin2019-04-092019-04-092019-02https://hdl.handle.net/11299/202437University of Minnesota Ph.D. dissertation.February 2019. Major: Electrical Engineering. Advisor: Sachin Sapatnekar. 1 computer file (PDF); xiv,, 112 pages.Over the past 50 years, complementary metal-oxide-semiconductor (CMOS) technology has developed aggressively and has undergone continuous scaling, as described by to Moore's Law. However, as transistor feature sizes approach the nanometer scale, there have been growing concerns with escalated power dissipation issues in very large scale integrated (VLSI) circuits, as well as device performance/reliability issues under process variations and aging. Meanwhile, emerging consumer electronic markets such as mobile and distributed computing, the internet of things, and autonomous driving platforms have posed various new challenges for the reliability and performance of electronic systems. While mainstream efforts have pushed forward scaling in CMOS technologies, there has been growing research interest in search for replacements for CMOS. Such efforts involve conceptualizing computational devices, based on new physics principles and new materials, that could serve as fundamental building blocks for new architectures, providing diversified computational functionality and offering better performance than the traditional CMOS-based paradigm. Among these beyond-CMOS technologies, spintronics is one of the most promising candidates for building next-generation logic devices. Spintronics takes advantage of an intrinsic property of electrons, spin, and develops the concept of state based on magnetism, which is a physical manifestation of electron spin. However, this new technology requires new simulation frameworks and design methods to be developed and deployed in order to propose and evaluate the potential of new spin-based devices, accounting for the impact of novel material properties that dictate the performance of these devices. Such frameworks can further be employed in determining the dependence of circuit performance on material and device parameters, and in optimizing these new technologies. The first part of the thesis provides a brief review of spintronics and explains a set of physical effects that are exploited to build spintronics-based devices descried in the later chapters. These include spin transfer torque (STT), which forms the basis for early spin-based logic devices, with its associated concepts of spin polarized current and non-local spin valve structure; the magnetoelectric (ME) coupling effect that provides low power and fast switching of magnetization in a ferromagnet (FM) with multiferroic material stacks; domain wall (DW) structures in FMs that can be used for logic transfer; and inverse spin orbit coupling (ISOC) effects, which offer convenient conversion between spin and charge states. The second part of the thesis develops performance optimization techniques for all-spin logic (ASL) devices. A framework for simulating ASL devices is first described, and a method for performance optimization through device sizing is developed. An algorithm for optimal device sizing, based on the geometrical dependence of the energy and delay for the ASL device, is then developed. The results of optimization on standard circuit benchmarks, implemented with ASL gates, are shown and the energy/delay trade-off relation is explored. The third part of the thesis introduces a new device, composite oxide magnetoelectric logic technology (CoMET), and the role played by this thesis research in developing the device. CoMET employs DW as the logic transfer medium and uses the ME coupling effect as well as its inverse effect to realize fast DW creation and detection. A composite structure with magnetization coupling existing between in-plane FM and perpendicular FM is added to the input end of the device in order to further lower the energy of the nucleation process. A detailed study of how this device nucleates a DW at the input end is conducted, and it is demonstrated how input nucleation can be performed in a fast and power-efficient way, leading to a high-speed, low-power CoMET device implementation. The pinning effect with random artificial defects of various sizes is discussed to show how such defects mitigate DW oscillation after nucleation. Such oscillations are seen in idealized defect-free DW structures that are typically simulated by researchers using micromagnetic simulators. The final part of the thesis studies the magnetoelectric spin orbit coupling (MESO) device that was recently proposed by researchers at Intel. The thesis presents a simulation framework and evaluates the performance of the device through detailed modeling, analysis and simulation. It is shown that when devices are cascaded, potential sneak path could corrupt the computation, and solutions to avoid this problem are proposed. To extend MESO to build general logic, two majority gate designs, based on a DW majority and a charge-based majority, are demonstrated and evaluated. It is shown under some scenarios, the charge-based majority gate may not provide correct output values and must be carefully designed to avoid these scenarios.enall spin logiclogic devicemagnetoelectric coupling effectspin orbit coupling effectspin transfer torque switchingSpintronicsThesis or Dissertation