Hybrid Binary-Unary Computing

Abstract

The binary number representation has dominated digital logic for decades due to its compact storage requirements. However, since the number system is positional, it needs to “unpack” bits, perform computations, and repack the bits back to binary (e.g., partial products in multiplication). An alternative representation is the unary number system representation. Using the unary number system representation, we can perform computation using “wiring network” or “wiring network + one level of simple logic”. However, for high resolution and especially for non-monotonic functions, the unary method is not scalable and suffers from large gate fanout requirements and high area~×~delay cost. In this work, we present a novel method that uses a hybrid binary-unary representation to perform computations. The core idea behind our method is to combine binary and unary encoding. We evaluate functions by first dividing the input range into a few sub-regions (binary), then performing computations on each region using the pure unary computing method, and finally repacking the unary data back to binary. The intuition behind our approach is that (1) preserving the higher bits of the binary data makes the encoding logarithmic as in conventional binary representation, and (2) dividing each function into a few sub-functions makes both the unary encoding and the unary function evaluation exponentially less costly. Experimental results on image processing applications show up to 85% saving in energy dissipation and 50% area reduction compared to the conventional binary and up to 30% saving in energy dissipation and 57% area reduction compared to the fully unary implementations. Moreover, We extend the idea to propose low-cost and high-performance approximate multipliers as the basic block of digital signal processing algorithms. We develop multiple digital signal processing applications using hybrid binary-unary basic blocks and evaluate the performance of these blocks in complex systems in terms of accuracy and hardware costs. Experimental results on a multi-channel Fast Fourier transform algorithm show up to 50% hardware resources reduction compared to prior Xilinx LogiCORE IP FFT implementation.