Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits

Abstract

Coupling capacitance is becoming increasingly problematic at the more advanced technology nodes and affects the timing and sign-off timeline of integrated circuits (ICs). As the coupling capacitance information is only available after the detailed routing phase, it can be a difficult task to make any major changes post detailed routing towards fixing issues caused by coupling effects that were unaccounted for. The goal of the project is to come up with an estimate of coupling capacitance for a given net before the detailed routing phase with the help of congestion maps. This information can be fed back to the detailed router which can help avoid routes that are susceptible to heavy coupling effects. The first part of this thesis explains why beforehand knowledge of a net’s coupling capacitance is crucial for a timely tape-out. This thesis revisits the Elmore delay model and extends the analysis to coupled RC structures. The notion of considering the coupling capacitance as a random variable is described to model the uncertainties that are introduced into the delay analysis which is performed ahead in time. The second part of this thesis illustrates how congestion analysis can provide valuable information about the severity of coupling effects. A method for the expedited extraction of estimated parasitics using congestion maps and global router solutions is presented. Modification to existing driving-point analysis techniques is suggested to accommodate coupled RC structures with probabilistic coupling capacitance. The last part of this thesis compares the delay metrics obtained from an open-source timing analyzer with the delay metrics obtained through methods described in this thesis for a given net.