A Reliability Analysis for Magnetic Tunneling Junction based Caches

Abstract

The spin transfer torque based magnetic random access memory (STT-MRAM) is a promising candidate as a potential SRAM replacement with impressive characteristics like non-volatility, zero leakage power, scalability, density and CMOS process compatibility, however it suffers from very high write current density. With ongoing scaling in MTJ, storage element of STT-MRAM, its very thin dielectric is subjected to very high stress raising reliability concerns amongst designers. The reliability of STT-MRAM is worsened as only worst case - highest voltage stress is considered for reliability estimation though multi-voltage domain is used for read and writes operation forcing designers to use slower clocks and lower voltages to meet lifetime criteria. In this work, we present a methodology which estimates reliability of MTJ based on device's Time Dependent Device Breakdown (TDDB) measurements considering circuit design parameters and architectural access patterns as design inputs. This methodology enables designers to estimate time dependent device failure probability and performance tradeoffs for generic and application specific designs. The effective Weibull distribution is predicted considering the stress due to multiple voltage's contributing stresses. A L2 cache reliability analysis is presented using Gem5 simulator to generate access patterns. The developed model is easily upgradable with technology scaling and can be extended to any device with its measured TDDB data.