Efficient Algorithms and Architectures with High Accuracy and Low Complexity for DSP Applications

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Efficient Algorithms and Architectures with High Accuracy and Low Complexity for DSP Applications

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2016-05

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In this thesis, we investigate efficient algorithms and architectures having high accuracy and low complexity for Digital Signal Processing (DSP) applications. We propose several design approaches to meet the requirements of real-time throughput and input-output latency, which are characteristic features of DSP applications. The approaches we propose include the use of efficient arithmetic representations, as well as creating structures with pipelining and parallel processing. The architectures also provide reduced hardware complexity by converting certain mathematical operations in the algorithms into simple DSP operations. The main topics are addressed in this thesis are the following: A complex multiplier using fused arithmetic units, a Fast Fourier Transform (FFT) processor using Algebraic Integer (AI) encoding, and adaptive wavelet transforms based on the lifting scheme. These topics are discussed in terms of the mathematical algorithms involved and their hardware implementations. To provide quantitative comparisons with previous work, we conduct fixed-point simulations with appropriate data wordlengths and implement architectures using field programmable gate array (FPGA) and Very Large-Scale Integration (VLSI) based platforms. Our results show improvements in performance and/or hardware complexity for the algorithms that are considered in this thesis.

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University of Minnesota Ph.D. dissertation.May 2016. Major: Electrical Engineering. Advisor: Gerald Sobelman. 1 computer file (PDF); viii, 97 pages.

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Yun, Sangho. (2016). Efficient Algorithms and Architectures with High Accuracy and Low Complexity for DSP Applications. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/181689.

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