This research work focuses on a hardware level implementation and verification of a multi-mode floating point conversion IP (Intellectual Property) capable of converting from the various floating point formats to the fixed-point format and vice-versa. This conversion can help improve the performance of a complex system with respect to speed, power consumption and cost and would also help in the design of an embedded system, where mostly fixed-point formats are used during the design, as it allows drastic savings in all traditional cost metrics. The proposed IP can work alongside a main processor or master which would be the main processing unit and would accept the input data and convert it to the required format and send it to the main processor. The results from the main processor can be fed again to the IP to convert it to the desired floating or fixed point format. The suggested design also includes the recently introduced half-precision floating point format (16-bit), which because of its advantages over the traditional single and double precision formats is finding use in many applications. All the conversion modules are compliant with the IEEE 754-2008 standard and also include the rounding modes and exception signals. The design is then verified using the concepts of Verification Methodology Manual (VMM) standard. The design and verification is performed using the SystemVerilog language.
University of Minnesota M.S.E.E. thesis. September 2015. Major: Electrical Engineering. Advisor: Gerald Sobelman. 1 computer file (PDF); viii, 81 pages.
Design and Verification of a multi-mode floating point conversion IP using SystemVerilog.
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