Layout-dependent stress is a significant source of variability in advanced VLSI technologies that impacts circuit performance. Mechanical stress affects transistor electrical parameters mobility and threshold voltage due to piezoresistivity and stress-induced band deformation, respectively. Unintentional sources of mechanical stress and intentional stress variability cause device performance to depend upon the underlying layout topology and its location in the layout. Advanced packaging technologies have exacerbated this class of variability by introducing new set of unintentional stresses in the layout. Consequently, circuit performance becomes highly placement dependent. The traditional paradigm of using pessimistic margins to account for variations can make meeting stringent design specifications a daunting task. Thus, it is imperative to capture the effects of layout dependent stress during circuit analysis. Evaluating circuit performance involves modeling the stress distributions in the layout accurately and translating the mechanical abstraction of the layout to circuit-level abstraction. This thesis develops scalable techniques to characterize the layout-dependent stress effects to quantify the ensuing circuit-level variations in path delays and leakage power. Based on this analysis, layout optimization strategies are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit performance variations. Thermal-stress effects are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. Analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing and leakage power consumption. A biaxial stress model is built, based on a superposition of 2D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate changes in transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performance induced by TSV stress. Finally, layout guidelines are presented that optimize circuit delays in 3D-ICs. Thermal stresses from shallow trench isolation (STI) are another major source of unintentional stress that affect bulk planar transistors in conventional and 3D integrated circuits. STI is employed to electrically isolate transistors and the amount of STI surrounding an active region depends upon the location of the neighboring transistors in the layout. An analytical model based on inclusion theory in micromechanics is employed to accurately estimate the biaxial stresses and the strains induced in the active region by the surrounding STI in the layout. The induced changes in mobility and threshold voltage changes are computed at the transistor level and then propagated to the gate and circuit levels to predict circuit-level delay and leakage power for a given placement. For 3D-ICs, the combined effects of STI and TSV are evaluated. In bulk technologies, intentional source/drain stressors are used to enhance transistor performance. In FinFET technologies, these stressors lose their effectiveness with reducing contacted gate pitch. Moreover, owing to the three dimensional nature of the FinFETs, the beneficial stress relaxes along the free-edges of standard cell layouts. Thus, the magnitudes of engineered mechanical stress depend upon the underlying layout topology. To improve circuit performance, a dual gate pitch technique is proposed, where standard cells with twice the gate pitch are selectively used on the gates of the circuit critical paths, at minimal area and power costs. A stress-aware library characterization is performed for FinFET-based standard cells by obtaining stress distributions using finite element simulations on a subset of structures. The stresses are then employed to create look-up tables for mobility multipliers and threshold voltage shifts, for subsequent performance characterization of FinFET-based standard cells. Finally, a circuit delay optimizer is applied using the dual gate pitch approach and is compared with an alternative gate sizing approach in 14nm/10nm/7nm technologies. Using a combination of gate sizing and the dual gate pitch approach, it is shown that the power delay product of FinFET-based circuits can be improved.