Browsing by Subject "FPGA"

Now showing 1 - 7 of 7
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    The Expansion of Digital Microfluidic Systems
    (2021) Anderson, Chase
    Digital microfluidics (DMF) is a technology that allows for movement and manipulation of liquid using electricity. By charging and discharging conductive pads upon a grid, one is able translate, split, and mix droplets to perform conventional wet lab operations. By minimizing handling time, chemical dangers, and laboratory wastes (e.g. pipette tips); DMF stands at the forefront of modern bio-chemical implementations. Most DMF prototypes/platforms utilize a single grid space, and this should change. In hopes to connect 4 ,16 , 64, or n-many grids for that matter; current DMF designs do not have required infrastructure. Each pad must be charged to upwards of 300 volts, so hardware, separate from the brains of the system, is required to facilitate normal operation. Like the heart, DMF platforms operate on beats and must be synchronous. Often, a microcontroller (Arduino, PIC, STM32) is used; however, microcontrollers operate sequentially, meaning each instruction given to the machine must execute one after the other. If one wished to parallelize the process of DMF, a separate computing paradigm must be used. Enter the FPGA (Field Programmable Gate Array). Being able to process multiple lightweight channels of data at a time, the FPGA enables the end user to have thousands if not millions of droplets moving synchronously across hundreds of grid systems. The research task was to find an elegant solution to the problem of parallelizing DMF systems using FPGAs.
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    FPGA based hardware-in-the loop controller for electric drives
    (2013-12) Chandrasekaran, Visweshwar
    Research and industrial implementation of Digital Signal Processor (DSP) based electric drive controllers continue to increase each year. DSP-based controllers are typically implemented on FPGA's or DSP microcontrollers by using proprietary development software. FPGA's have advantages over DSP microcontrollers for control due to their parallel processing capability and flexible architectures. An FPGA based motor control system was developed using the Matlab Simulink Toolbox: Xilinx System Generator for DSP. A customized library was developed that has many common blocks used in the development of drive models. An FPGA board based on Xilinx's Spartan 6 family was also developed which can be used with a PC for hardware-in-the-loop co-simulation. The controller can be operated in a DSP-based Electric Drives Laboratory that is currently using a dSPACE rapid prototyping system. This is hence a cost-effective replacement that still provides the full processing power of dSPACE controllers.
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    Methodologies and tools for yield improvement of field-programmable logic architectures.
    (2009-12) Maidee, Pongstorn
    According to the international technology roadmap for semiconductors (ITRS) predictions, controlling manufacturing yield is going to be a challenging task in future technologies. It was shown that the effective yield of the future field programmable gate arrays (FPGAs) will be too low to make a profit. Several FPGA yield improvement techniques have been proposed such as clustering, spare column and node covering. However, the challenges of future fabrication technologies are so great that these techniques cannot fully address high yield demands of the future. Thus, novel techniques should be explored. We propose three approaches for FPGA yield improvement in this thesis: one adds redundant components to the FPGA architecture to tolerate permanent faults. Another technique speeds up a synthesis technique used in a rewiring engine to allow for replacement or enforcement of faulty wires in a circuit. The third technique uses a search space pruning technique to speedup the optimization of FPGA architecture development. The proposed yield improvement techniques can be applied in conjunction with other existing techniques, resulting in an effective framework for FPGA yield improvement. Chapter 2 addresses fault tolerant FPGA architectures that introduce redundancies in the architecture to replace faulty components. A methodology is proposed for estimating the effectiveness. Effectiveness of existing defect-tolerant schemes such as clustering, spare column and node covering for contemporary FPGA architectures. Furthermore, a number of new schemes to further improve yield are proposed in Chapter 2. Several techniques for tolerating defects in switch boxes were also introduced. The results show that the spare column scheme is very effective in maintaining a satisfactory yield. However, our studies show that to maintain reasonable yields, the number of spare columns must increase in the future. We also show that having redundancy for routing channels increases the absolute yield, but the benefit is outweighed by the area overhead for some types of routing channels. As a result, we show that redundancy must be judicially applied to the routing architecture to result in high yield numbers. Chapter 3 addresses yield improvement at the synthesis level. Circuit rewiring is proposed in this thesis to enhance effectiveness of existing approaches, namely customization and design-specific approaches. The success of rewiring depends on both the quality and speed of the rewiring engine. Among several rewiring techniques that have been purposed, a Set-of-Pairs-of-Functions-to-be-Distinguished (SPFD)-based rewiring was shown to be more effective than the others both in theory and practice. However, due to its longer runtime, it is not a viable rewiring technique. A novel algorithm is proposed to avoid expressing SPFDs explicitly. Instead, a few satisfiability problem (SAT) instances are solved, allowing rewiring of one instance in the order of milliseconds. The experimental results show that our proposed technique's runtime is only a fraction of that of a conventional one and it scales well with the number of candidate wires considered. The existing SPFD-based rewiring approaches also limit where a new wire can be added. We present a theory that allows us to add a new wire virtually anywhere in the circuit structure. An algorithm based on this theory is also presented. Experiments show that the number of wires which can be rewired increases significantly and the number of alternate wires for a given wire also increases. Chapter 4 deals with designing a family of FPGA chips. The goal of this chapter is to minimize area across a large number of designs. Minimizing area in turn helps improve yield. We formulate the family selection process as an FPGA family composition problem and propose an efficient algorithm for solving it. The formulation can capture an increasingly complex specialized functional block selection problem for FPGA families. The technique is applied to an architecture similar to Xilinx Virtex FPGAs. The results show that a smart composition technique can significantly reduce the expected silicon area. The benefit of providing specialized blocks can also be investigated using the technique and thus it can be used as an important tool for determining the benefits of specialized blocks for future FPGAs.
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    Reconfigurable computing platform for small-scale resource-constrained robot.
    (2010-01) Kim, Byung Hwa
    Specific applications often require robots of small size for reasons such as costs, access, and stealth. Small-scale robots impose constraints on resources such as power or space for modules, but they still require great functionality to do challenging tasks such as surveillance, urban search and rescue, application-specific sensing, robotic assembly, etc. This thesis develops a reconfigurable computing platform for small-scale resource-constrained robots that allows rapid deployment of available hardware and software for a specific task. Resource-adaptive control is introduced where control parameters can be changed with respect to the resource usage such as power consumption, area, or execution speed, as well as plant change. The use of a Field Programmable Gate Array (FPGA) is essential in providing the flexibility in hardware for both sensor interfacing and hardware-accelerated computation. In this study, reconfiguration is achieved by two steps; static reconfiguration and dynamic reconfiguration. This thesis utilizes reconfiguration technology in order to solve issues on resources and functionality. Prior to executing a task, a robot needs to be equipped with necessary sensors and actuators. This thesis introduces a new scheme of configuring a robot system before deploying a robot into a field, which is called static reconfiguration. Static reconfigurability of the hardware manifests itself in the form of a "morphing bus" architecture that permits the modular connection of various sensors. It is a novel sensor bus in the fact that no bus interface circuitry is required on a sensor side - the bus "morphs" to accommodate the signals of the sensor. Dynamic reconfiguration or run-time reconfiguration is performed in order to maximize the resource utilization in terms of power, area and speed while the robot is executing tasks. A software architecture for hardware/software dynamic reconfigurability is proposed and it provides for the reallocation of hardware and software resources at run time as the mobile, resource-constrained robots encounter unknown environmental conditions that render various sensors ineffective. A novel strategy to search a configuration tree is presented and metrics for cost functions in the tree are introduced. Resource-adaptive controller can modify control parameters, or change the order of a plant model, or even choose a different control algorithm by examining resource utilization during dynamic reconfiguration.
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    Timing Driven Analytical Placement for FPGA
    (2015-09) Agashiwala, Nimish
    Conventional Simulated Annealing (SA) based placement methods for FPGAs give best results in terms of wirelength and critical path delay. The runtime for these SA based methods is directly proportional to the total number of cells to be placed. In case of modern multi-million gate FPGAs, SA based methods for placement dominate the total runtime in the FPGA CAD flow. In this thesis, we propose a new fast and efficient timing driven analytical placement engine targeted at global placement for FPGAs followed by low temperature SA for detailed placement. Our global placement engine uses quadratic programming approach to minimize the wirelength and dynamic net weights based on timing criticality between the blocks to minimize the critical path delay. The placement engine proceeds by iteratively partitioning the placement area and making the Configurable Logic Blocks (CLBs) move near each partition's Center of Gravity (CG). After each iteration, to calculate the timing criticality between each CLB, they are snapped to physical grid locations. The placement engine uses this timing feedback to update the net weights and calculate new coordinates for the CLBs in the next iteration. We employ a spiral legalization method in the end to obtain a legalized placement which then undergoes low temperature Simulated Annealing in VPR to give comparable or better critical path delay and 8.7% bad overall wirelength after placement. Experimental results of 20 largest MCNC benchmark circuits show that our global placement engine outperforms the state-of-the-art academic placer VPR 7.0 in terms of runtime by 30% on an average, making it scalable and provides an overall similar QoR in terms of critical path delay.
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    Wirelength-driven Analytical Placement for FPGA
    (2015-08) Upadhyay, Satya Prakash
    With increasing complexity of modern circuit, FPGA demands to be dealt with good CAD algorithm and suitable architecture to meet the lower non-recurring engineering cost and faster time-to-market. Placement is one of the crucial steps among them, as it decides time for implementing FPGA, routing resources and power consumption by digital circuits. Our research is centered on the placement algorithm for FPGA design. Simulated Annealing (SA) being the most popular among all the placement methods for quality results, takes huge compile time to implement larger circuits with the current new architectures. Researchers try to find a way for getting similar or better results with less run time. Based on the requirement, placement can be wirelength driven, timing driven and path driven. There are alternate ways of placement which are based on min-cut algorithm and analytic placement, and take less time. We targeted to optimize wirelength while doing placement using Gordian method in multiple iteration to get similar results as that of well-known academic research tool for FPGA - Versatile Place and route (VPR). Each iteration divides a subspace in four partitions and applies linear and bounding constraint to solve for quadratic optimization. We bypassed the placement methodology of VPR with our placement algorithm of analytical placement, implemented in MATLAB, and then fed back the output of our placer to the VPR flow for detailed placement and routing. We compare our results of placement and routing using 20 MCNC benchmarks and homogeneous VTR benchmarks with the VPR flow. Our MATLAB placer is faster by 38% with the expense of wirelength quality. It gets 1% better wirelength with 11% increase in runtime compared to the whole VPR placer after low temperature simulated annealing based final detailed placement.