Process variations have become increasingly important as feature sizes enter the sub-
100nm regime and continue to shrink. Both logic and memory circuits have seen their
performance impacted due to these variations. It is increasingly difficult to ensure that
the circuit manufactured is in accordance with the expectation of designers through sim-
ulation. For logic circuits, general statistical static timing analysis (SSTA) techniques
have emerged to calculate the probability density function (PDF) of the circuit delay.
However, in many situations post-silicon tuning is needed to further improve the yield.
For memory circuits, embedded DRAM (eDRAM) is beginning to replace SRAM as the
on-die cache choice in order to keep the scaling trend. Although techniques exist for
statistical analysis of SRAM, detailed analysis of eDRAM has not been developed prior
to this thesis.
In this thesis, we provide techniques to aid statistical analysis for both logic and
memory circuits. Our contribution in the logic circuits area is to provide robust and
reliable, yet efficient post-silicon statistical delay prediction techniques for estimating the circuit delay, to replace the traditional critical path replica method that can generate
large errors due to process variations during the manufacturing process. We solve this
problem from both the analysis perspective and the synthesis perspective. For the
analysis problem, we assume that we are given a set of test structures built on chip, and
try to get the delay information of the original circuit through measurement of these test
structures. For the synthesis problem, we automatically build a representative critical
path which maximally correlate with the original circuit delay. Both of these approaches are derived using variation aware formula and use SSTA as sub-steps. They capture the
delay variation of the original circuit better than the traditional critical path replica
approach and eliminates the need to perform full chip testing for the post-silicon tuning
In response to the growing interest in using eDRAM-based memories as on-die cache,
in the memory analysis area we provide the first statistical analysis approach for the
cell voltage of eDRAM. We not only calculate the main body of the PDF for the cell voltage, but also specifically look at the tail of this PDF which is more important to
ensure quality design due to the highly repetitive nature of the memory systems.
We demonstrate the accuracy and efficiency of our methods by comparing them with
Monte Carlo simulations.