As communication speeds have increased, high speed and resolution analog-to-digital converters (ADCs) have become necessary. ADCs have traditionally relied on comparing an input voltage to a reference voltage and digitizing the result. The increased speed of operation requires faster processes, which in turn limit the usable input voltage range due to breakdown voltage limitations. The work presented in this thesis studies two aspects of ADCs and possible alternate implementations to address existing limitations.
A sample-and-hold amplifier (SHA) is a common first stage for ADCs. At high frequencies, the SHA provides valuable timing relief to subsequent stages. Biasing of the high speed circuits consumes valuable headroom in low voltage circuits, limiting operation of existing architectures to supply voltages of at least 1.8V. An alternative architecture is presented that allows reduced supply voltages to be used.
An alternative core ADC architecture is also discussed. The implementation chosen utilizes a time measurement system that quantizes time instead of voltage. A phase delay proportional to the input voltage is first generated. This signal is then quantized using a time-to-digital converter. The use of active devices in the clock path is eliminated, allowing for increase operation speed while delay generation is accomplished with varactors, allowing for large voltage swings on the input signal.