Prohibitive ASIC mask costs and stringent time-to-market windows have made FPGAs attractive implementation platforms in recent years. Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. However, providing such great flexibility comes at a high cost in terms of area, delay and power. In the first part of this thesis, we propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. This mixture is obtained from careful profiling of benchmark circuits. The result is about 30% reduction in leakage power consumption, 5% smaller area and 20% shorter delays, which translates to 25% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced.
With constant scaling of process technologies in the ultra deep sub-micron regime, chip design is becoming increasingly difficult due to process variations. The FPGA community has only recently started focusing on the effects of process variability. In the second part of this thesis, we propose CAD and architecture techniques to mitigate the impact of process variations in FPGAs. We present a variation-aware router that optimizes statistical timing criticality. We then propose a modification to the clock network to deliver programmable skews to different flip-flops. Finally, we combine the two techniques and show a 9X reduction in yield loss that translates to a 12% improvement in timing yield. When the desired timing yield is set to 99%, our combined statistical routing and skew assignment technique results in a delay improvement of about 10% over a purely deterministic approach.
Another challenge with aggressive technology scaling is to ensure the reliability of circuits. Issues with circuit reliability manifest as intermittent failures caused by random particle strikes or permanent failures due to thermal stress. In the third part of this thesis, we develop computationally efficient techniques for analyzing and optimizing reliability of circuits subject to transient particle strikes. We propose a hybrid method that combines exact symbolic analysis with probabilistic measures to estimate reliability. We use such measures in rewiring and gate-sizing based methods to optimize reliability. We study trade-offs involved in terms of area, power and delay when optimizing reliability. Our proposed approach offers a speedup of 56X compared to a Monte Carlo simulation based approach with only a 3.5% loss in accuracy. Our rewiring-based optimization framework improves reliability by 10% along with area and power improvements of 14% and 18% respectively. When we combine the rewiring and gate sizing based optimization techniques, reliability is improved by 17% with modest area and power overheads.
In the final part of this thesis, we propose a fast thermal simulation technique for single-processor and chip multi-processor systems. Our technique can be used to estimate thermal stress in modern processors efficiently. A fast and accurate estimation of thermal stress in a system is critical to improving its reliability by preventing catastrophic permanent failures. Our proposed technique of evaluating temperatures across the chip is based on moment matching and moves most of the computation offline. Our temperature computation technique offers a speedup of 441X when compared to a conventional technique based on a Backward-Euler approach with average and maximum errors of 0.89 C and 2.7 C respectively. We observe that lateral heat conduction in the active and substrate layers are significant only for a short distance. We leverage this information to further improve the efficiency of thermal estimation and achieve a speedup of 1900X.
University of Minnesota Ph.D. dissertation. Major: Electrical Engineering. Advisor: Dr. Kia Bazargan. 1 computer file (PDF); xii, 172 pages. Ill. (some col.)
Sivaswamy, Satish Barghav S.
Architecture and CAD techniques for optimizing FPGAs and reliability of integrated circuits..
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