Many existing algorithms use the divide-and-conquer paradigm to partition a large problem into smaller sub-problems to reduce time complexity and provide better solutions. One application would be used to divide one large VLSI circuit design into two more manageable pieces in order to manufacture the design into integrated circuit packages. Even though there have been attempts on implementing parallel versions of these algorithms in software, no serious attempt has been made to design hardware implementations of these algorithms. A promising approach to harness the power of FPGAs for complex algorithms is the use of randomized algorithms. By using a randomized "guess-and-check" process called the Monte Carlo method to find optimal partitioning solutions, this project aims to improve upon existing software partitioning algorithms. An FPGA will provide random numbers at the bit-by-bit level. A PowerPC will make use of these random numbers to divide the VLSI design into two distinct parts. After thousands of iterations and potential solutions, the best solution is retained for use. The hope is that guessing at a solution thousands of times could be a better method of optimization than running a complex algorithm.