Interconnect design and signaling methods play an important role in modern VLSI systems by providing a communication medium between distant points having low latency, small energy consumption and robustness against noise. An important figure of merit for monolithic buses is power consumption, which is a function of bus topology, technology parameters and the signaling methods used. It has been reported in the literature that buses may consume more than half of the total power budget of a chip. This thesis develops a set of signaling methods and coding techniques to ameliorate this power problem.
A multilevel signaling scheme is chosen in which more than two voltage values are used to represent the transmitted data. This approach incorporates both bus multiplexing and reduced voltage swings to achieve the low-power goal. A comprehensive analysis of energy consumption for voltage-mode, multilevel signals on a nanometer technology bus is presented. An accurate, transition-dependent model for multilevel buses is proposed which allows simplified calculation of the bus energy consumption. This energy model is then applied, together with physical optimization of the on-chip interconnect structure, to achieve highly energy-efficient on-chip bus communication. The results show that significant energy savings can be achieved compared to traditional binary signaling methods.
Next, a novel technique called Bus Transform coding for multilevel signals is proposed, which is an extension of the traditional Bus-Invert coding of binary signals. Simulation results show that this technique can achieve reductions in the average power consumption compared to an uncoded multilevel bus.
Finally, this thesis shows, through the use of trellis diagrams and the Viterbi algorithm, that Bus-Invert coding is optimal for a sequence of data values transmitted over a binary bus.