Power management in SRAM based caches was increasingly popular for the fact that leakage power consumption of cache hierarchies is comparable to the power consumed by logic cores. There are a number of power management techniques proposed using circuit design and architectural techniques to reduce leakage power in SRAM based memories. Existing techniques closely monitor the behavior of sub-array building blocks in caches and dictates when to enter and exit sleep mode. This global sleep control policy is conservative and inefficient as it requires a closed loop architectural support to make low power decisions. In this work, we introduce aggressive power management schemes which has local decision logic that maintains parts of the sub-array in sleep mode even during active phases of operation thus saving leakage and idle power. We propose and implement three micro-architectural techniques named DRAM-like refresh, column based sleep and bitline segmentation in the 128kb SRAM sub-array building block to adopt additional power management schemes that are enabled per idle cycle basis. In active mode, each of these methods achieve leakage and dynamic power reduction by activating only a portion of the sub-array while during sleep mode, DRAM-like refresh trades off sub-threshold and dynamic refresh power to save idle data retention power. Our evaluations show that these methods on an average can achieve ~20\% more leakage savings during sleep and up to ~75\% more average power savings during active and idle operation. The implementation comes with an area overhead of ~4-5\% without any impact on the memory occupancy ratio. Later, we perform architectural evaluations to exploit memory access pattern and reconfigure the power management control circuitry to dynamically operate based on the demand of the application during active and idle states thus achieving additional power savings compared to static schemes. We also recommend combinations of these adaptive power management schemes for different levels of memory hierarchy after profiling the memory access pattern of various workloads.