This thesis discusses the design of the receiver front-end for software defined radio (SDR) based cognitive radio applications. Two aspects of SDRs for cognitive radios are distinguished: signaling and spectrum sensing. Narrowband wide tuning signaling architectures and instantaneous wideband spectrum sensing architectures are identified as candidates for feasible SDR implementations. Several architectures and circuit im- plementations are reviewed. Wide tuning range, low phase noise frequency synthesizers for signaling, and RF samplers and signal processors for spectrum sensing are identified as critical circuit design blocks.A number of voltage controlled oscillator (VCO) techniques for wide-tuning range, and low phase noise frequency synthesis techniques are developed. Wide-tuning range techniques based on switched inductors are proposed as a way to design inductor- capacitor (LC) VCOs with wide-tuning ranges that maintain a good phase noise and power dissipation performance over the entire tuning range. Switched inductor VCOs are analyzed in detail, and a design framework is developed. Optimized capacitor array design techniques for wide-tuning ranges are discussed. Based on these techniques, mea- surements from two prototype designs are presented, that achieve tuning ranges of 87% and 157% in measurement. They also maintain good phase noise, power consumption, and figure of merit (FOM) over the entire tuning range.In addition, a new family of VCOs that achieve superior phase noise is introduced. This set of novel topologies are based on linearized transconductance using capacitive feedback techniques. They achieve higher amplitudes of oscillation, and consequently, a superior phase noise performance. A wide tuning range is also maintained. The VCOs are analyzed, and detailed measurement results from a design prototype are presented. For spectrum sensing, the design of CRAFT (Charge Re-use Analog Fourier Trans- form): an RF front-end channelizer for software defined radios (SDR) based on a 16 point analog domain FFT is described. The design relies on charge re-use to achieve 47dB average output SNDR on a 5GS/s input, and consumes only 12.2pJ/conv. These numbers represent orders of magnitude improvement on the work reported previously in literature. The thesis also briefly discusses the modeling of circuit non-idealities in CRAFT, and outlines circuit techniques for mitigating these. These design principles enable this implementation to achieve a large dynamic range even at high speeds. Ad- ditionally, these techniques can be easily extended to improve the performance of other passive switched capacitor designs.