PLL-based frequency synthesis is a common method for developing highly stable
oscillators.The need for this type of synthesizer that can operate at non-integer
multiples of a reference oscillator is growing. Delta-sigma modulators used to
control the division ratio in PLL-based fractional-N frequency synthesizers help to
meet the growing need for synthesizers operating at non-integer multiples. A PLLbased
fractional-N frequency synthesizer using a delta-sigma modulator to control
the division ratio was analyzed at the system level and implemented at transistor
level. The system level analysis consisted of understanding the effect of the deltasigma
modulator on spurious tone reduction in the synthesizer output. Circuit
blocks were then designed individually at transistor level. Results of the delta-sigma
output and the overall synthesizer were then discussed. The synthesizer achieved a
start-up speed of 4sec. The in-band phase noise performance was -82 dBc/Hz at 3 MHzoffset from the carrier.
University of Minnesota M.S. thesis. July 2012. Major: Electrical and computer engineering. Advisor: Dr. Hua Tang. 1 computer file (PDF); v, 55 pages.
Soldner, Thomas M..
Design of a Delta-sigma fractional-N PLL frequency synthesizer at 1.43GHz.
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