The parametric shifts or circuit failures caused by Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time Dependent Dielectric Breakdown (TDDB) in CMOS transistors have become more severe with shrinking device sizes and voltage margins. These mechanisms must be studied in order to develop accurate reliability models which are used to design robust circuits. Another option for addressing aging effects is to use on-chip reliability monitors that can trigger real-time adjustments to compensate for lost performance or device failures. The need for efficient technology characterization and aging compensation is exacerbated by the rapid introduction of process improvements, such as high-k/metal gate stacks and stressed silicon.
Much of the device aging data gathered for process characterization is obtained through individual probing experiments. However, probing stations are expensive, and they have other drawbacks such as limited timing resolution. In order to resolve these issues, several on-chip systems have recently been proposed to measure device aging. In this thesis I will present five unique test chip designs that we have implemented for this purpose.
Performing reliability experiments with on-chip circuits provides us with several advantages, in addition to avoiding the use of expensive probing equipment. First, using on-chip logic to control the measurements enables much better timing resolution. This is critical when interrupting stress to record BTI measurements, as this mechanism is known to partially recover within microseconds or less. We will also see that a digital beat frequency detection system allows us to measure ring oscillator frequency shifts with resolution ranging down to a theoretical limit of less than 0.01% . That mix of speed and resolution is not possible with standard off-chip equipment. Next, standard logic can be used to control tests on several devices in parallel, resulting in a large experiment time speedup when monitoring statistical processes. Utilizing these benefits to obtain accurate CMOS aging information would allow manufacturers to avoid wasteful overdesign and frequency guardbanding based on pessimistic degradation projections, and hence more fully realize the benefits of CMOS scaling.
University of Minnesota Ph.D. dissertation. April 2010. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF);xvii, 141 pages.
Keane, John P..
On-Chip circuits for characterizing transistor aging mechanisms in advanced CMOS technologies..
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